Crosstalk Timing Window Analysis and Prevention Techniques

In the previous two articles, we have discussed signal integrity, crosstalk, crosstalk mechanisms, the parasitic capacitances associated to interconnects, crosstalk noise, crosstalk delay and its effects. In this article, we will discuss the timing window analysis of crosstalk and the prevention techniques of crosstalk. 

Timing Window Analysis

Crosstalk timing window analysis is based on the concept that we need to consider a timing window on which the aggressor has an effect on victim net. This analysis method is more accurate and less pessimistic as compare to the infinite arrival window where we assume that aggressor can switch at any time. Figure-1 shows the switching window of a victim net. If the aggressor net switching window overlaps with the switching window of the victim net then only delay of victim cell get affected else it will not get affected. 

Figure-1: Timing window analysis

Here we have shown the out of phase case where delay increases due to the crosstalk effect, but this concept is equally applicable in case of in-phase transition where delay will decrease. 

Timing widow concept is also applicable in the crosstalk noise analysis also. In the case of multiple aggressors effect on a victim net, the analysis will be carried out based on the timing widow only. This is a more realistic approach.

Crosstalk prevention techniques

There are various ways to prevent crosstalk, some of the well-known techniques are as follow.

 

1. Increase the spacing between aggressor and victim net:

Figure-2: Effect of net spacing on crosstalk

Figure-2 shows that by increasing the spacing between aggressor and victim net we are ultimately reducing the coupling capacitance between them as the capacitance is inversely proportional to the distance between them. So by increasing the spacing crosstalk will decrease.

2. Shielding of nets:

Figure-3 shows the shielding technique used to prevent crosstalk. Generally, we insert a shielding net between the victim and the aggressor net. The shielding net is connected to strong VDD or VSS. 

Figure-3: Shielding of a net 

By shielding a net the two things will happen, one is the direct coupling capacitance between the aggressor and victim net will vanish and secondly the shielding net will remain at a constant logic so there are no chances of crosstalk.

The above two techniques will prevent the crosstalk but it has an impact on the area.  Both techniques will require more area to route them.

3. Upsizing the victim cell:

If we increase the drive strength of the victim cell it will not be easy to affect by the aggressor net. 

4. Downsize the aggressor cell:

Higher the drive strength of aggressor cell, higher is the impact of crosstalk on the victim. So by reducing the drive strength we can reduce the crosstalk effect. 

Crosstalk timing window analysis is based on the concept that we need to consider a timing window on which the aggressor has an effect on victim net.

Thank you. 

Crosstalk Noise and Crosstalk Delay - Effects of Crosstalk

In the previous article, we have discussed signal integrity, crosstalk, crosstalk mechanisms and the parasitic capacitances associated to interconnects. In this article, we will discuss the effects of crosstalk. Crosstalk has two major effects:

1. Crosstalk glitch or crosstalk noise
2. Crosstalk delta delay or crosstalk delay

Crosstalk glitch

In order to explain the crosstalk glitch, we will consider the following two cases. There might be many more similar cases.

Case-1: Aggressor net is switching low to high and victim net is at a constant low 

Figure-1: Crosstalk glitch (Raise)

In this case, the aggressor net switches from logic 0 to logic 1 and victim net is at constant zero as shown in the figure-1. Now consider the node A, node V, Mutual capacitance Cm and path from A to V. As node A start switching from low to high, a potential difference across the mutual capacitance get developed and the mutual capacitor Cm starts charging.  During this event, there is some leakage current which starts flowing from node A to node V through the mutual capacitance Cm due to the leaky nature of mutual capacitance. This leakage current will raise the potential of node V, which creates a raising spike or raising glitch on the victim net as shown in figure-1. The magnitude of this voltage or height of glitch will depend on the various factors which will be discussed later.

So, whenever one net switches from low to high and other neighbouring net is supposed to remain constantly low, will get affected by the switching net and have a glitch on it. Now let's discuss the case-2 which is similar to the case-1. 

Case-2: Aggressor net is switching high to low and victim net is at a constant high

Figure-2: Crosstalk glitch (Fall)

In this case, the aggressor net switches from logic 1 to logic 0 and victim net is at constant high logic as shown in the figure-2. Now consider the node A, node V, Mutual capacitance Cm and path from V to A. As node A start switching from high to low, a potential difference across the mutual capacitance gets developed and the mutual capacitor Cm starts charging through node V to node A.  During this event, there is a leakage current which starts flowing from node V to node A through the mutual capacitance Cm due to the leaky nature of mutual capacitance. This leakage current will drop the potential of node V, which creates a falling spike or falling glitch on the victim net as shown in figure-2. 

So, whenever one net switches from high to low and other neighbouring net is supposed to remain constantly high, will get affected by the switching net due to the mutual capacitance and have a falling glitch on it.

In case-1 and case-2 we have seen that if one net is switching and another neighbouring net is at constant logic and if they have mutual capacitance between them, the other net may get affected and that net may have a sudden raising or falling bump or spike. such a spike on victim net is called crosstalk glitch or crosstalk noise. Figure-3 shows the situations when there is a raise glitch or fall glitch. 

Figure-3: Raising and Falling glitch in crosstalk

Effects of crosstalk glitch

Does every glitch unsafe? The answer is it depends on the height of glitch and the logical connection of the victim net. If the height of glitch is within the noise margin low (NML), Such a glitch is considered as a safe glitch. If the glitch height is above the noise margin high (NMH), such a glitch is considered as a potentially unsafe glitch. In the case of glitch height is in between NMH and NML, this is an unpredictable case. Figure-4 shows the CMOS inverter transfer characteristics and Noise margins.

Figure-4: CMOS transfer characteristics and Noise margin

As the technology node shrinks, the supply voltage also gets lowered down.  In lower supply voltage, noise margin will be lesser. If noise margin is lesser it is more prone to have a potentially unsafe glitch. Figure-5 will help to understand this fact. 

Figure-5: Safe and unsafe glitch based on glitch heights

Figure-5 shows safe and unsafe glitch based on glitch heights. Safe glitch has no effect on the next logic of the victim net and the logic of the victim net will be treated as correct logic. But in other cases, the victim net's logic may be treated as wrong logic due to the glitch and a wrong data will be propagated which might cause the failure of chip. Generally reset pins of memory is a constant logic and if such pin's net has an unsafe crosstalk glitch, memory might get reset. Many other situations may occur which may cause chip failure due to the unsafe glitch.

But there are some cases where there are no effects of crosstalk glitches. For example, consider there is a two-input AND gate whose one input is tied at constant 0 and at the other input nets there is crosstalk happening. so whatever the effects of crosstalk, the output always will be Zero. similar cases are for many combinational logic where there would be no effects of crosstalk. Again in case of glitch height is within the range of noise margin low.  

Crosstalk glitch height

Crosstalk glitch will be safe or unsafe depends on the height of crosstalk glitch and the logic pin from which the victim net is connected. So let's investigate the factors on which the crosstalk glitch height depends. 

Crosstalk glitch height depends basically on three factors:

1. Coupling capacitance

2. Aggressor's drive strength

3. Victim's drive strength

Closer the nets will have greater coupling capacitance. More the capacitance will have larger glitch height. Drive strength of the aggressor and victim driver will also affect the glitch height. The high drive strength of the aggressor net will impact more the victim net. If the drive strength of the victim net is high, then it will not be easy to change its value, that means lesser will be the effect of crosstalk.

It was all about the crosstalk glitch or crosstalk noise, Now let's move the second effects which is crosstalk delta delay or crosstalk delay. 

Crosstalk Delay

Crosstalk delay occurs when both aggressor and victim nets switch together. It has effects on the setup and hold timing of the design. Crosstalk delay may cause setup and hold timing violation. So it is important to do crosstalk delay analysis and fix the timing considering the effect of crosstalk. 

Crosstalk could either increase or decrease the delay of a cell depending upon the switching direction of aggressor and victim nets. We will take two cases one when both nets switch in the same direction (high to low or low to high) and other both the nets switch in opposite direction and will analyze the effect of crosstalk delay.

Case-3: Aggressor and victim net switch in opposite directions

Let's consider aggressor net switches from low to high logic and victim net switches from high to low (opposite). as shown in figure-6. 

Figure-6: Crosstalk delay due to opposite direction switching

As node A start transition from low to high at the same time, node V starts switching from high to low. There will be a potential difference from node A to V as half of the transition happened. There is a coupling capacitance between A and V so aggressor node will try to pull up the victim node. This will affect the smooth transition of the victim node from high to low and will have a bump after half of the transition and this will result in an increase in the transition time of the victim net. Figure-7 shows the transition of nets. After crosstalk, the delay of the cell will be increased by Δ and new delay will be D + Δ.

Figure-7: Crosstalk delay (increase) 

Case-4: Aggressor and victim nets switch in the same direction

Let's consider aggressor net switches from low to high logic and victim net also switches from low to high (same direction). as shown in the figure-8. 

Figure-8: Crosstalk delay due to same direction switching

As node A start transition from low to high at the same time, node V also starts switching from low to high. Suppose aggressor net has high drive strength and so fast transition, a potential difference from node A to V will be developed after half of the transition happened. There is a coupling capacitance between A and V so aggressor node will try to fast pull up the victim node. This will affect the smooth transition of the victim node from low to high and will have a bump after half of the transition and this will result in a decrease in the transition time of the victim net. Figure-9 shows the transition of nets. After crosstalk, the delay of the cell will be decreased by Δ and the new delay will be (D - Δ).

Figure-9: Crosstalk delay (decrease)

Effects of crosstalk delay

There are various effects of crosstalk delay on the timing of design. It could make unbalance a balanced clock tree, could violate the setup and hold timing. In this section, we will discuss some of them.

Effect on clock tree: 

Crosstalk could unbalance a balanced clock tree. Crosstalk delay may increase or decrease the delay of clock buffers in the clock path and a balanced clock tree could be unbalanced as shown in the figure-10. 

Figure-10: Effect of crosstalk delay on clock tree

Let's suppose the latency of path P1 is L1 and for the path P2 is L2. If the clock tree is balanced then L1 must be equal to L2. Now due let's assume crosstalk delay occurs and it affects a clock buffer in clock path P2. Then now L1 will no more equal to L2 and now clock tree is not balanced. Here we have considered only one clock buffer got affected by the crosstalk delay but in reality, the effect could be in many places.

 Effect on setup and hold timing:

Crosstalk delay can violate the setup timing. Figure-11, shows the data path, launch clock path and capture clock path. 

Figure-11: Effect of crosstalk delay on setup timing

For setup timing, data should reach the capture flop before the required time of capture flop. So if there is an increase of delay in the data path or launch clock path it may cause setup violation. Setup violation may also happen if there is a decrease in delay on the capture clock path. These effects of crosstalk delay must be considered and fixed the timing. 

Hold timing may be violated due to crosstalk delay. Figure-12, explains the situations where the hold time could violate due to crosstalk delay. 

Figure-12: Effect of crosstalk delay on hold timing

If there is a decrease in the delay of any cells in the data path and launch clock or there is an increase of delay of cells in the capture clock path due to crosstalk delay, It may result in the hold timing violation. Such cases must be considered and fix the timing. 

This article is being too long, so we will stop here and will continue the remaining part, timing window analysis and crosstalk prevention techniques in the next article.

Thank you.

Signal Integrity and Crosstalk effect in VLSI

“According to a research conducted by Collett International Research Inc., one in five chips fails because of the signal integrity.”

In this article, we will discuss a very important issue of VLSI design called signal integrity and crosstalk which are responsible for the failure of many ASICs now a day. We will discuss signal integrity and crosstalk in this article. The effects of crosstalk and prevention techniques will be discussed in the next two articles. 

Signal Integrity:

Signal could be defined as information in the form of wave/impulse which is used for communication between two points. In Digital form, it is either in state 1 (high) or in state 0 ( Low) as shown in the figure-1 below. 

Figure-1: Digital signal

By definition integrity means “complete or unimpaired”. Or We can say that maintaining the actual form of anything over time without any distortion. 

So signal Integrity could be defined as replication of the entire signal while transmitting from one point to another without any distortion in its quality. Or In a broader perspective, we can say that Signal Integrity is the ability of an electrical signal to carry information reliably and resist the effects of high-frequency electromagnetic interference from nearby signals.

Signal Integrity addresses two concerns in digital design

•Timing of signal – Does the signal reach the destination when it is supposed to?

•Quality of signal – When the signal reaches, is it in good condition?

“Timing” is everything in high-speed digital design. 

 

So the goal of Signal Integrity is to ensure reliable, high-speed data transmission from one point to another point inside the chip through the metal lines. Increased data rate and lower technology node, Maintaining signal integrity is a big challenge.

In a nutshell,  if the signal travels through a net without any distortion, Signal Integrity is high, If there are lots of noise added on it / distortion occur/delay occurred, Signal Integrity is less.

Signal Integrity may be affected by various reasons, but major reasons are:

1.Crosstalk (Delay and Noise )

2.Ground bounce

3.IR Drop

4.Antenna effect

5.Electromigration

In next section we will discuss Crosstalk issue.

What is Crosstalk?

Crosstalk could be defined as a phenomenon in which logic transmitted in one net creates undesired effects on its neighbouring nets. Or in another world, we can say switching of a signal in one net can interfere in the neighbouring net, which is called crosstalk.

When a signal switches, it may affect the voltage waveform of a neighbouring net. The switching net is typically identified as the “aggressor” and the affected net is the “victim.”    Figure-2 shows a typical arrangement of aggressor and victim net. 

Figure-2: Aggressor and Victim nets

Crosstalk is a very severe effect especially in lower technology node and high-speed circuits and it could be one of the main reason of chip failure. In the next section, we would discuss the crosstalk mechanism in VLSI Design.

Crosstalk mechanism

Crosstalk occurs via two mechanisms:

1. Inductive Crosstalk
2. Electrostatic crosstalk

Inductive crosstalk occurs due to mutual inductance between two nets. A varying current in a net creates a varying magnetic field around the net. A varying magnetic field can either radiate energy by launching radio frequency waves or it can couple to adjacent nets. Such coupling of the magnetic field is called inductive crosstalk. 

Electrostatic crosstalk occurs due to mutual capacitance between two nets. The electric voltage in a net creates an electric field around it. If the electric field is changing, It can either radiate the Radio waves or can couple capacitively to the adjacent net. Such coupling of the electric field is called electrostatic crosstalk. 

Out of two mechanisms explained here, Electrostatic Crosstalk mechanism is more significant and problematic than Inductive crosstalk. So in this section, we will talk about Electrostatic crosstalk. 

Parasitic capacitances related to Interconnects

The main reason of crosstalk is the capacitance between the interconnects. So in this section, we will investigate various capacitance associated with metal interconnects. Figure-3 shows the various parasitic capacitances get formed inside an ASIC (click on image for a better view).

Figure-3: Various capacitances associated with interconnects

 

After the FEOL (Front Line Of Line) fabrication, a thick SiO2 insulating layer is deposited all over the substrate before metal-1 (M1) layer fabrication. The insulating layer between M1 and substrate acts as a dielectric and forms a capacitance between M1 and substrate. this is called substrate capacitance (cs). M1 is patterned and the unwanted metal areas are etched away and again empty regions are filled with SiO2. So there is the formation of parasitic capacitance between two neighbouring M1 nets (same metal layers) which is called lateral capacitance (CL). M2 layer is fabricated above M1 followed by SiO2 layer. So there is the formation of interlayer capacitance  (CI) between any two conjugative metal layers. Interlayer capacitance can be formed not only conjugative metals but also the metals far away to each other, like M2-M4 or M2-M5. The value of all these capacitance depends on two factors, common area and the gap between them. These capacitances are directly proportional to the common area between them and inversely proportional to the gap between them.

Summary

This article explained the signal integrity, crosstalk, crosstalk mechanisms and parasitic capacitances related to interconnects. The effects of crosstalk are crosstalk glitch or crosstalk noise and crosstalk delay or delta delay. In the next article, we will discuss crosstalk glitch and crosstalk delay. 

 

Thank you.

Antenna Prevention Techniques in VLSI Design

In the last article, we have discussed the antenna violation. How antenna violations occur, what is the mechanism to occur antenna effect or Plasma Induced Gate oxide damage. So in this article, we will discuss the solution part of the antenna effect, that is how to prevent the antenna violations.

How to prevent antenna violation?

Before discussing the prevention, let's recall the root cause of the antenna effect, then it will be easy to understand the prevention techniques. Antenna effect occurs mainly due to the excessive accumulation of charges on a metal interconnect connected to the gate of transistors during the plasma etching of metal interconnect. The amount of accumulated charge depends on the area of the metal interconnect connected to the gate. The excessive accumulated charges get discharged through the thin gate oxide and it causes permanent damage in the gate oxide. 

Based on the above-mentioned reason for antenna violation, the following three approaches can be applied to prevent the issue. The first method is to reduce the amount of charge accumulation and this can be achieved by reducing the area of metal interconnect connected to the gate of a transistor. The second method is to increase the gate area so the ratio (metal area)/(gate area) becomes lesser than the permitted maximum metal to gate area ratio. This can be achieved by attaching the floating gates to the related net. The third method is to provide an alternative path to get discharge the accumulated charges on the gate of the transistor that is the addition of an antenna diode.

Three basic techniques are to prevent antenna violations are:

1. Metal hopping 
2. Floating gate attachment
3. Antenna diode 

Now it's important to know about antenna rules and violation. We will come back to this point after seeing the antenna rules.

Antenna Rules

A process design kit (PDK) comes with some rules deck files. The antenna rule set is a part of the rule deck. All the rule set must be checked before the tapeout. In antenna rules, the most common rule is the antenna ratio.

• Antenna ratio is the ratio of the metal area connected to the gate to the total area of the gate
• Antenna ratio is defined in the following form:

Antenna area / Gate area < Maximum antenna ratio

Example of antenna rule violation

Consider three cases here:

In case-1 suppose metal-2 has length = 200um as shown in the above figure and width of metal =1um. This metal wire is connected to the gate of a transistor. The transistor is having gate width = 2um and length = 0.6um. 

Therefore, Total metal area = 200x1 = 200um^2

                       Total gate area = 0.6 x 2 = 1.2um^2

                    Therefore, antenna ration = 200/1.2 = 166.2

In case-2 suppose the situation is same but the metal-2 is connected to 4 such transistors instead of 1.

Therefore, Total metal area = 200x1 = 200um^2

                       Total gate area = 0.6 x 2 x 4= 4.8um^2

                    Therefore, antenna ration = 200/4.8 = 41.66

In case-3 suppose the metal-2 is broken into two parts of 50um each and connected through metal-3 as shown in the figure below. Such a connection is called metal hoping. 

Now, Total metal-2 area = (50x1)x2 = 100 um^2                       

          Total gate area = 0.6 x 2 = 1.2 um^2

           Therefore, antenna ration = 100/1.2 = 83.33

Suppose the antenna ratio is given 100 in the antenna rule. So out of the three cases above explained, Case 1 is violating the antenna rule and case 2 and case 3 is not violating the antenna rule. 

How to fix the antenna violations

Above example shows that If we increase the gate area by increasing the number of connected transistors, it will reduce the antenna ratio. Another approach could be by reducing the antenna area, that breaks the metal and insert the jumper in between. So we can reduce the antenna ratio in two ways:

1. Reduce the antenna area - Jumper insertion or metal hoping
2. Increase the gate area - by dummy transistor insertion

Antenna Checks (Physical Verification)

• Antenna checks verify the layout against the antenna rules of rule decks. There are many more checks need to perform before tapeout like DRC, ERC, LVS etc and these all are collectively called physical verification of layout. 
• Physical verification tools (like Calibre, Assura, IC Validator) varifies the antenna rule for all the layers for which antenna rule is applicable.
• Antenna rules strongly depend on the process nodes.

Fixes of antenna violation

1. Jumper Insertion or Metal hoping

Best way to break the lengthy metal into small pieces and using jumpers route them through other metal layers as shown in the above figure (click on the image see the large image). This process is called jumper insertion of metal hoping.

2. Dummy transistor insertion

The effective gate area can be increased by inserting dummy transistors as shown in the above figure. This will decrease the antenna ratio and help to meet to antenna rule. In a practical scenario, we can add a floating inverter/buffer. We attach the input of buffer/Inverter to the concerned net and leave the output floating. This will increase the effective gate area and help to overcome the antenna violation.

3. Antenna diode insertion

• Antenna diode -Reverse biased
• Placement location - Near the gate terminal
• Plasma etching 400-800 degree Celsius
• High Temperature – Diode is thermally unstable
• During plasma etching - Reverse saturation region
• At reverse saturation region – like a resistive path
• Normal operation -40 to 125 degree Celsius
• Standard cell – Antenna diode cell
• Single terminal standard cell, N+ on Psub.

Various techniques for antenna prevention have been explained in this article. I tried to explain these in the simplest way and hope you are able to understand these thoroughly. 

Thank you.