Latch-up Prevention in CMOS Logics

Before discussing the prevention techniques of Latch-up issue, let's recall the key factor of the latch-up issue first. Following two factors are important for the latch-up issue.

• High resistance of n-well and p-substrate
• β1 x β2 >  1 

                                                Figure-1: Latch-up formation

Figure-1 shows the parasitic BJT formation which causes latch-up. n-well and p-substrate resistance can be reduced by increasing the doping but it will degrade the device performance drastically.  But we can cut down the gains of parasitic BJT (β) and prevent the latch-up issue. Some popular techniques for latch-up preventions are as bellow.

• Guard ring 
• Well tap cells
• Isolation trench
• Epitaxial layer
• Retrograde well doping 
• Combination of epitaxial layer and retrograde well doping
• FDSOI Technology
• ESD protection techniques

1. Guard ring: 

                                                        Figure-2: Guard Ring

If Vout goes bellow the VSS and the diode between drain and p-substrate of nMOS become forward bias, electrons from drain start injecting from to substrate and collected by the body of pMOS. This cause a current from in the opposite direction of electron flow. which ultimately triggers the Qp transistor as shown in the figure-1. Now to break this chain, two sets of n+ implant in n-well, p+ implant on p-substrate added in between nMOS and nMOS as shown in the figure-2. These will collect the electrons injected from the drain of nMOS and prevent the current flow from the drain of nMOS to the body of pMOS. Which stops triggering the Qp BJT.

Similarly in case of the Vout goes above the VDD and drain of pMOS start injecting holes in n-well and goes and collected by the body of nMOS. This lead to the trigger of Qn BJT. But by adding the guard ring these holes will be collected by the guard ring and stop the latch-up.

2. Well tap cells: 

In tapless standard cell design to prevent the latch-up, we need to tap the n-well to VDD and p-sub to VSS. These well tap cells tap the n-well to VDD and p-sub to VSS. Figure-3 shows the crosssection of tapless cell and figure-4 show the layout of well tap cell and tapless standard cell.

                                        Figure-3: Cross-section of tap and tapless cell

Figure-4: Layout of tapless cell and well tap cell

The well tap cells are placed in the standard cell row in the regular interval as per the maximum distance rule define in technology library. 

3. Oxide trench isolation: 

In this technique, nMOS and pMOS have insolated using the buried oxide and oxide trench. A horizontal buried oxide created deep inside and vertical oxide trenches are created later and connected both together to separate the n-well and p-substrate. The oxide trenches are isolator in nature so oxide trench stops the formation of the PNPN device. A cross-section of oxide trench isolation is shown in the figure-5.

Figure-5: Crosssection of a trench isolation

4. Epitaxial Layer: 

In this technique, a low doped p-epitaxial layer (known as P-) grown over the P-substrate (called P+). The P- epitaxial layer provides a low impedance path for minority carrier which prevents the latch-up triggering. This technique is also called P on P+. A cross-section epitaxial layer has shown in the figure-6.

Figure-6: Crosssection of CMOS using epitaxial layer

The only problem with this technique is, it's a sophisticated process to grow the epitaxy layer. Another alternative is we can use the epitaxy wafer for this purpose.

5. Retrograde Well Doping : 

In normal n-well doping process, the doping concentration is highest at the surface and it decreases as the depth of well increases. But in the retrograde well doping process, there is very precise control of doping concentration over the depth and we have peak doping concentration at deep inside the n-well, not at the surface. A doping profile of normal doping and retrograde well doping is shown in figure-7.

                                                Figure-7: doping profile of retrograde well doping

A retrograde well doping is done at the bottom of normal n-well as shown in the figure-8. This region has a high doping concentration and creates a low resistance path. The body connection which is taken from N+ doping is extended to this high dopped region. So there is the formation of low resistive path bellow the n-well which stops the triggering of PNPN device. A cross-section view of retrograde well doping has shown in figure-8.

Figure-8: Retrograde well-doped CMOS

6. Combination of the epitaxial layer and retrograde well doping : 

We can use a combination of the epitaxial layer and retrograde well doping together both the techniques together which is also a very effective way to prevent the latch-up issue but the process is a bit complex.

7. SOI Technology : 

In SOI (Silicon on Insulator) technology an oxide layer comes bellow the source-drain doping and stop the parasitic BJTs formation. So SOI technology completely eliminates the latch-up issue. A cross-section of CMOS in SOI technology has shown in figure-9.

                                            Figure-9: CMOS in SOI Technology

We can use a combination of the epitaxial layer and retrograde well doping together both the techniques together which is also a very effective way to prevent the latch-up issue but the process is a bit complex.

These are the ways to prevent latch-up in CMOS technology. Each technique has its own pros and cons. 

Thank You!

Latch-up issue in CMOS Logic | Latch-up effect in VLSI

What is a latch-up issue in CMOS design?

In the simplest way, the latch-up issue can be defined as a formation of a direct path from VDD to GND terminal in the design, which will cause a huge current flow between the power and ground terminal.

Latch-up Formation: 

Inside a CMOS (Complementary Metal Oxide Semiconductor)  circuit, two parasitic BJT (Bipolar Junction Transistors) get formed and connected in such a way that these BJT form a PNPN device or SCR (Silicon-Controlled Rectifier) or Thyristor. Formation of the PNPN device is shown in the figure below.

As shown in the above figure, a pMOS device is formed inside a nwell and a nMOS device is formed on the p-substrate region. If we see the region below the source or drain of the pMOS device, source or drain is formed with P+ implantation then nwell come and bellow the nwell there is p-substrate. So a parasitic PNP BJT formed here, whose emitter is the source of the pMOS, the base is the nwell and collector is p-substrate. In a similar manner a parasitic NPN BJT has formed near the nMOS device, whose emitter is the source of nMOS , the base is the p-substrate and collector is nwell.

Both this BJT are connected to each other in such a way that they form a PNPN device. The base of PNP BJT is connected to the collector of NPN BJT and base of NPN BJT is connected to the collector of NPN BJT.

A PNPN device is normally in OFF state and there are minimal current or no current flow through it. But once the PNPN device is get triggered by its gate signal, a large current starts to flow through it and it continues to flow even if the gate signal removed. The figure below shows the terminals of the PNPN device and its characteristics.

Technically latch-up is the phenomena of activating the parasitic BJTs in a CMOS circuit which forms a low impedance path between the power and ground terminals. This low impedance path draws a large current and heats up the IC (Integrated Chip) which cause permanent damage of IC.

Latch-up Triggering: 

PNPN device formed inside the CMOS can be triggered by various means. Once the PNPN device is triggered by any means, the latch-up event will start. Some of the main reasons are as below.

• Noise at the output terminal
• ESD (Electrostatic Discharge) event
• Ionizing radiation 

Consider the above figure and suppose the output voltage has gone beyond the VDD due to noise, then it will forward bias the transistor between drain terminal and nwell of pMOS. Once this junction is forward bias, P+ region will start injecting hole to nwell, and these holes will be collected by body contact of nMOS as it is connected to GND. So this event will start flow of current from the drain of pMOS to the body of nMOS. Due to the flow of above-mentioned current, there will be a voltage drop between the source terminal of nMOS and the substrate below it. It will forward bias the pn junction between substrate and source of nMOS. This will again start injecting electrons from N+ source to the substrate, which will be collected by body terminal of pMOS which is connected to the VDD and shown in red dotted line. So eventually a chain will start and next source terminal of pMOS and nwell will be forward bias. In this way both the BJT has turned on and latched up. 

In a similar way, if vout goes below the VDD , first the junction between the drain of nMOS and substrate will be forward bias, and it will make the junction between the source of pMOS and nwell forward bias and again this will further make the junction between the source of nMOS and substrate forward bias and both the BJT will be turned on and latch-up will occur.

Once the latch-up occurred in CMOS design, lots of current start flowing directly from VDD to GND and will cause the failure of chip. So we must protect our chip from latch-up. In the next article, we will discuss the method to prevent the latch-up issue. 

Thank you!