Physical Verification Interview Questions : Question set - 4

 

Code: QLCM2Y062020PV

General Questions

1. What are lambda based design rules?
2. What is nm in 10nm technology node?
3. Do you know about under bum density?
4. Any prior experience of PnR?
5. How do you import design in PnR?
6. Why ID layers have been given in lower nodes (10nm)?
7. Why nwell continuity is required?
8. Have you done scripting?
9. Can you write an algorithm?
10. What is drive strength?
11. Why the industry is moving towards lower technology nodes like 7nm or 5nm?
12. What are challenges seen in lower technology node?

Physical Only Cell

1. What is a tap cell?
2. What are the uses of tap cells?
3. What is Endcap or boundary cell?
4. How does halo cell avoid DRCs t boundary? What is there inside the halo cell that prevents DRCs ? How it is different from standard cells?
5. What difference it makes when you add halo cell in boundary instead of standard cell?
6. Why is the standard cell nwell bigger in size and slightly coming out of the standard cell? It is not so in halo cell.
7. Suppose a tap cell is covering 10um distance, then where should the next tap cell be placed in the same row?
8. How do you calculate the distance between tap cells in a row?

DRC

1. What kind of base DRCs have you encountered?
2. Have you seen DRCs between the standard cell and filler cell of the same height?
3. What is Endcap or boundary cell?
4. How did you solve DPT (double patterning)?
5. What metal DRC have you encountered?
6. What kind of via DRCs have you come across?
7. What will happen if GDSII has DRC unfixed and sent to Fab?
8. Is there any problem if the ID layers are interchanged?
9. Which ID layer is manufactured first?

LVS

1. Have you analyzed the LVS result or someone else analyzed the result and you fixed?
2. Apart from short and opens what errors have you seen in LVS and How did you resolve?
3. What kind of issues are seen in LVS?
4. What is priority errors in LVS? Could there be false violations?
5. Where does the tool start to calculate LVS from?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks, Karthik for sharing and helping people.

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Physical Verification Interview Questions : Question set - 3

 

Code: INTL2Y052020PV

Floorplan

1. What are the inputs for floorplan?
2. In order to make sure integration is DRC clean, what rules or guidelines need to be followed at the floorplan stage?
3. Can we abut macros on par boundary?
4. How will judge the congestion between two IPs during floorplan stage without actual routing being done?
5. Apart from IP alignment, what analysis have you done?
6. What do you check at the placement stage? 

Physical Only Cell

1. What are the types of physical only cells in the design?
2. In what stage are physical only cells placed in the design?
3. Why are different types of physical only cells needed in design?

Latch-up

1. Are you aware of latch-up in CMOS, can you elaborate?
2. Explain how the parasitics are formed?

Antenna Effect

1. What is the antenna effect?
2. How can antenna effect be solved?
3. Why metal jogging is done in the higher layer during antenna fixing?
4. Which diode is used as an antenna diode?
5. What parameters are considered while choosing the cutoff voltage of an antenna diode?
6. How do you decide the number of diodes that needs to inserted for the failing net?
7. On what basis have you inserted diodes?
8. If M12 is the highest metal in the design and it has antenna, how do you fix it?
9. Have you heard of nwell antenna?
10. Can power net have an antenna effect?
11. Can the antenna diode be placed in a different power from that of the affected cell?
12. What is the impact of placing the antenna diode on timing?
13. Where are the antenna diode terminals being connected?
14. Voltage or current that is causing the antenna effect?
15. How the gate area can be increased in antenna affected cell?
16. How are you adding the antenna in antenna affected cell?
17. What is the drive strength?
18. What is the W/L ratio?
19. Which layers are most susceptible to antenna violations, higher or lower layers? 
20. How do you handle antenna in clock net?

ECO Implementation

1. What are types of ECOs?
2. Where the ECOs generated and given to you or you prepared ECOs?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks Karthik for sharing and helping people.

Physical Verification Interview Questions : Question set - 2

Code: INTL2Y052020PV

General

1. What is done to solve congestion in lower and higher metal?
2. How cell spreading helps in routing congestion?
3. Cell spreading is done on what basis?
4. What is DFM and why is it needed?
5. What happens if DFM is not met?
6. What are the inputs to GDSII file?
7. What is crosstalk, Which checker is used to detect the crosstalk?
8. What is the difference between gate level netlist and layout netlist?
9. How does a MOSFET work?
10. What does the length of channel refer to?
11. Explain transfer characteristics of a CMOS Inverter.

DFM

1. Why Density needs to be maintained?
2. What kind of densities are there?
3. How do you know the density of each cell?
4. If there are 100 plus density windows, then how to fix it?
5. What happens if there are min or max density during fabrication?
6. Whats are the projects you have done related to synthesis and Physical Design?

DRC

1. What is DRC?
2. Will the design be clean if halos are places properly in design?
3. What are the types of DRC?

LVS

1. What is LVS What it checks for?
2. What are the inputs and outputs of LVS?
3. What are hierarchical shorts?
4. What are the inputs to generate the OASIS file?
5. What is the full form of OASIS?
6. What is the difference between ICC LVS and ICV LVS?
7. In what format does the tool calculate the LVS?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks Karthik for sharing and helping people.