Antenna Prevention Techniques in VLSI Design

In the last article, we have discussed the antenna violation. How antenna violations occur, what is the mechanism to occur antenna effect or Plasma Induced Gate oxide damage. So in this article, we will discuss the solution part of the antenna effect, that is how to prevent the antenna violations.

How to prevent antenna violation?

Before discussing the prevention, let's recall the root cause of the antenna effect, then it will be easy to understand the prevention techniques. Antenna effect occurs mainly due to the excessive accumulation of charges on a metal interconnect connected to the gate of transistors during the plasma etching of metal interconnect. The amount of accumulated charge depends on the area of the metal interconnect connected to the gate. The excessive accumulated charges get discharged through the thin gate oxide and it causes permanent damage in the gate oxide. 

Based on the above-mentioned reason for antenna violation, the following three approaches can be applied to prevent the issue. The first method is to reduce the amount of charge accumulation and this can be achieved by reducing the area of metal interconnect connected to the gate of a transistor. The second method is to increase the gate area so the ratio (metal area)/(gate area) becomes lesser than the permitted maximum metal to gate area ratio. This can be achieved by attaching the floating gates to the related net. The third method is to provide an alternative path to get discharge the accumulated charges on the gate of the transistor that is the addition of an antenna diode.

Three basic techniques are to prevent antenna violations are:

1. Metal hopping 
2. Floating gate attachment
3. Antenna diode 

Now it's important to know about antenna rules and violation. We will come back to this point after seeing the antenna rules.

Antenna Rules

A process design kit (PDK) comes with some rules deck files. The antenna rule set is a part of the rule deck. All the rule set must be checked before the tapeout. In antenna rules, the most common rule is the antenna ratio.

• Antenna ratio is the ratio of the metal area connected to the gate to the total area of the gate
• Antenna ratio is defined in the following form:

Antenna area / Gate area < Maximum antenna ratio

Example of antenna rule violation

Consider three cases here:

In case-1 suppose metal-2 has length = 200um as shown in the above figure and width of metal =1um. This metal wire is connected to the gate of a transistor. The transistor is having gate width = 2um and length = 0.6um. 

Therefore, Total metal area = 200x1 = 200um^2

                       Total gate area = 0.6 x 2 = 1.2um^2

                    Therefore, antenna ration = 200/1.2 = 166.2

In case-2 suppose the situation is same but the metal-2 is connected to 4 such transistors instead of 1.

Therefore, Total metal area = 200x1 = 200um^2

                       Total gate area = 0.6 x 2 x 4= 4.8um^2

                    Therefore, antenna ration = 200/4.8 = 41.66

In case-3 suppose the metal-2 is broken into two parts of 50um each and connected through metal-3 as shown in the figure below. Such a connection is called metal hoping. 

Now, Total metal-2 area = (50x1)x2 = 100 um^2                       

          Total gate area = 0.6 x 2 = 1.2 um^2

           Therefore, antenna ration = 100/1.2 = 83.33

Suppose the antenna ratio is given 100 in the antenna rule. So out of the three cases above explained, Case 1 is violating the antenna rule and case 2 and case 3 is not violating the antenna rule. 

How to fix the antenna violations

Above example shows that If we increase the gate area by increasing the number of connected transistors, it will reduce the antenna ratio. Another approach could be by reducing the antenna area, that breaks the metal and insert the jumper in between. So we can reduce the antenna ratio in two ways:

1. Reduce the antenna area - Jumper insertion or metal hoping
2. Increase the gate area - by dummy transistor insertion

Antenna Checks (Physical Verification)

• Antenna checks verify the layout against the antenna rules of rule decks. There are many more checks need to perform before tapeout like DRC, ERC, LVS etc and these all are collectively called physical verification of layout. 
• Physical verification tools (like Calibre, Assura, IC Validator) varifies the antenna rule for all the layers for which antenna rule is applicable.
• Antenna rules strongly depend on the process nodes.

Fixes of antenna violation

1. Jumper Insertion or Metal hoping

Best way to break the lengthy metal into small pieces and using jumpers route them through other metal layers as shown in the above figure (click on the image see the large image). This process is called jumper insertion of metal hoping.

2. Dummy transistor insertion

The effective gate area can be increased by inserting dummy transistors as shown in the above figure. This will decrease the antenna ratio and help to meet to antenna rule. In a practical scenario, we can add a floating inverter/buffer. We attach the input of buffer/Inverter to the concerned net and leave the output floating. This will increase the effective gate area and help to overcome the antenna violation.

3. Antenna diode insertion

• Antenna diode -Reverse biased
• Placement location - Near the gate terminal
• Plasma etching 400-800 degree Celsius
• High Temperature – Diode is thermally unstable
• During plasma etching - Reverse saturation region
• At reverse saturation region – like a resistive path
• Normal operation -40 to 125 degree Celsius
• Standard cell – Antenna diode cell
• Single terminal standard cell, N+ on Psub.

Various techniques for antenna prevention have been explained in this article. I tried to explain these in the simplest way and hope you are able to understand these thoroughly. 

Thank you.

Antenna Effect in VLSI | Antenna Issue in Physical Design

Gate Oxide of a MOS transistor is the most sensitive part of a MOS device. Special care needs to be taken during fabrication of ASIC to protect it from any damages during fabrication steps and ASIC operation too. The antenna effect is a phenomenon that may cause damage to the gate oxide of MOS during the fabrication process especially due to the plasma etching process. In this article, we will investigate the antenna effect phenomena in detail and the reasons which are responsible for this effect.

What is the Antenna Effect?

The term Antenna Effect might not give you the right intuition about the actual effect it may lead you to think about electromagnetic radiation or transmitter-receiver concepts but here the case is different. So It has another popular name which is called "Plasma Induced Gate Oxide Damage" which provides the right intuition about the effect. As this name itself indicates that this is an effect caused by the Gate Oxide Damage due to the Plasma Etching process during the fabrication process of VLSI chips.  

Although the antenna effect occurs during the fabrication stage of the chip especially at the time of plasma etching but the prevention mechanism should be set in the physical design stage. The fabrication laboratory provides the antenna rule file which must be checked and designed should be cleaned as per the antenna rule during the physical signoff stage.

In fabrication flow first FEOL (Front End Of Line) is fabricated which involves the fabrication of all MOS transistors.  Once the FEOL fabrication is done BEOL (Back End Of Line) fabrication starts which involves the fabrication of metal interconnects. Antenna effect comes into the picture while BEOL fabrication. 

In IC manufacturing process Plasma etching process is used to fabricate the metal interconnects. Plasma etching is a dry and anisotropic etching process, used for selective etching. Plasma contains high energetic ions and radicals which get collected by the metal interconnects while the etching process of metals. Figure-1 shows the structure of MOS and collection of plasma by the interconnect.

Figure-1: MOS structure and plasma etching 

The amount of charge accumulation depends on the surface area of interconnect. These collected ions increase the potential of the interconnect and if the interconnect is connected to the poly gate, ultimately the potential of the gate will increase. Due to this increased potential of the gate, a drainage path may be formed through the gate oxide to substrate to balance this extra accumulated charge on the gate. If the amount of charge accumulation is high, this drainage path through the gate oxide may either breakdown the gate oxide which leads to permanent damage of MOSFET or may create charge trapping in the gate oxide which further leads to many side effects like early gate oxide breakdown, mobility degradation and threshold voltage shift. 

Gate oxide damage occurs basically due to plasma etching of interconnects connected to the gate, that's why this effect is also called "Plasma Induced Gate Oxide Damage" or "Antenna Effect". The metal interconnect which collects the plasma (ions) and is connected to the gate is basically termed as the antenna. Here it is important to know the fabrication process of interconnects which is explained in the next section.

Interconnects Fabrication Process

Over the polysilicon, a layer of dielectric is deposited and then cuts are made for the contact. Over the contact, Metal-1 is deposited and patterned and etched the extra metal and filled the whole region by the dielectric. Now before fabricating the metal-2, cuts are made in dielectrics for Via-1 and filled with Via-1 then over the via-1 Metal-2 is deposited. Again in the same way Metal 2 is etched and filled with dielectrics. This process is repeated as many times as the number of metal layers is there. At the end of all the metals processed, A PSG encapsulation is done as shown in the figure.

There are basically three steps are performed to process any metal layer after the corresponding via/contact is fabricated. 

• Deposition

• Etching

• CMP

In the first step metal is deposited, In the second step the unwanted area of metal is etched away and in the third step, CMP (Chemical Mechanical Policing) is done.

Now let's talk more about the etching process. There are basically two types of etching processes is there, one is called wet etching with chemicals and the second is a dry etching with gasses. Dry etching provides complete anisotropic etching in which the lateral etching rate is zero. The most popular plasma etching is a dry etching process which is explained in brief in the next section. 

Plasma Etching 

Here the plasma etching process will be explained in brief just to understand the process. Plasma etching involves a high-speed stream of plasma of an appropriate gas mixture being shot at the sample. The plasma source is known as etch species are either charged ions or neutral atoms or radicals. During the etching process, plasma generates volatile etch products from the chemical reaction between the target material and the reactive species generated by the plasma. A basic setup of plasma etching has shown in the figure below.

Figure-3: Plasma etching setups

Figure-4: Plasma etching process in semiconductor fabrication

Both top and bottom electrodes are equal in size and parallel to each other. Bottom electrode holds the wafer and it is grounded. Due to the application of RF voltage and high pressure (P = 100mT to 1T) a plasma is set up between the two electrodes. High energetic electrons react with gas molecules and give various reactive species, neutral species and ions. Neutral species provide chemical etching and ions provides physical etching and a combination of reactive species and ions provides Ion Enhanced Etching.

We will discuss the prevention techniques of the Antenna effect in the next article. 

Thank you.