Interview questions asked for DFT Engineer (Fresher) - Question Set - 07

 

Code: INTL0Y032021DFT

This interview was held for the position of DFT Engineer with 0 years of experience. I personally felt the questions are good and generic which will help the freshers in other domains too.

Round-1:

1) Differences between MOSFET and FINFET ?
2) Puzzle:  A blind man walking in a desert has 2 red pills and 2 blue pills with him. He has to take one red pill and one blue pill each per day. How can he do that correctly?
3) Limitations of MOSFET
4) Puzzle: If a man climbs 15 m well. He climbs 4 m every day and slips 3 m . How many days it takes for him to get outside of the well?
5) What is set up time and hold time?
6) What is set up time and hold time violations?

7) What is metastability and do you know its physical significance?
8) What is a critical path?
9) How can you improve the timing?
10) How can you fix the setup time violations?
11) Implement a 2:1 mux for AND gate?
12) Draw the timing diagram of half adder?
13) What is blocking and non-blocking assignments?

14) What is synchronous and Asynchronous reset?

15) Why do we need DFT and what do you mean by that ?
16) Explain briefly the methods of DFT?
17) Why do you need to make flip flops initialized in an ad hoc technique?
18) What are controllability and observability?
19) If you fabricate a full adder and do the functional test and verify outputs are correct, then do you still require DFT also?
20) What is BIST?
21) What is JTAG?
22) Difference between verification and DFT?
23) What is yield?
24) Explain your course works and the projects.
25) Difference between RAM, ROM.
26) What is DMA?

Round-2:

1) Short channel effects in MOSFET.
2) Brief about JTAG.
3) Any insight into BSDL.
4) What are the different faults that occur while fabrication?
5) What is bridging fault?
6) What is fault collapsing?
7) Draw a D-flipflop along with a timing diagram.
8) What is Stuck at faults?

9) What do you mean by clock skew?
10) Is Hold time dependent on clock frequency?
11) Is clock skew an advantage or not?
12) Current technology node used in industry?
13) Is set up time-dependent on clock frequency?
14) Why do you need a reset in flip flop?
15) What is the multicycle path?
16) Any tools for DFT?

17) Why DFT is in the front end?
18) VLSI design flow.
19) OR gate using 2:1 mux
20) How to do if statement synthesis?
21) How do a case statement in Verilog synthesis?
22) What is Inferred latch?
23) List out a few Power optimization methods in STA.

My sincere thanks to the teamVLSI member who shared this genuine question set with us. If you feel such questions help you in your interview preparation, You are encouraged to share your interview questions with us at teamvlsi2014@gmail.com and help the community as you are getting help.

Written Test Question for Physical Design Engineer: Question Set - 6

 

 Code: ALTRN0Y112020PD

Some companies take a written test sometimes to shortlist the candidates before the interview process. This is a common process if the applicants are large in numbers. In such written test, the format is MCQ and some short questions. 

We are very thankful to one of our follower who has appeared in this test and shared these questions based on memory. The purpose of sharing this question is only to provide the right guidance to the candidate who is going to appear in such a written test. I would encourage all the freshers to practice these question for their future test/Interview. I would also encourage to find the answer to these question either by own. There is no sense of proving the answer to these questions here. But if someone finds any question really difficult to solve and open discussion in the comment section. 

1. Hold slack equation 

2. Setup slack equation

 

3. When did hold analysis depends on the frequency of the clock 

a) half cycle path

b) single cycle path 

C) multicycle path 

d) it never depends 

4. While doing OCV which things are considered for setup analysis 

a) max launch path delay and min capture path delay

b) min launch path delay and max capture path delay 

c) max launch and capture path delay

d) min launch and capture path delay 

5. How to fix EM effect 

a) decreasing the space between metal layers 

b) decreasing straps 

c) increasing drive strength of the driver 

d) increasing space between metal layers 

6. Why do we add tap cells 

a) to maintain well continuity 

b) to prevent latch up  

c) to prevent DRC's 

d) all of the above 

7. Why do we add metal fillers 

a) to ensure etching properly 

b) to ensure density issues 

c) to increase the area of the chip 

d)to ensure well continuity 

8. If the schematic has 11 and layout is 10 nets then, what might be reason 

a) opens 

b) shorts

c) ERC

d) all of the above 

9. Numerical problem related to finding clock frequency 

10. Numerical problem related to finding slack 

11. High positive skew leads to

a) setup violation 

b) hold violation 

c) DRcs

d) all of the above 

12. In VLSI Design, CMP stands for? 

13. Numerical problem to find setup slack 

14. Nand and Nor gate logic diagram SOP forms

15. Setup uncertainty increases from placement to CTs

a) true 

b) false

c) based on SDC 

d) based on clock frequency 

16. Only clearing LVS leads to the proper functioning of the chip 

a) true 

b) false 

17. Numerical problem related to reg to reg data path delay calculation 

18. A CMOS circuit consumes only a significant amount of power during 

a) static state 

b) when cooling 

c) when warming

d) all of the above 

19. Routing congestion depends on which factors

a) ratio of required layers and available layers 

b) ratio of available and required 

c) depending on availability of metalayers 

d) none of the above 

20. Question related to ground bounce, power bounce and glitch 

21. Value of threshold voltage depends on

a) doping concentration 

b)distance between source and drain 

c) temperature 

d) all of the above 

22. Why we reorder scan chains during placement stage?

23. For multi-voltage blocks which power cells are used 

a) isolation cells

b) retention cells 

c) level shifters 

d) all

24. Which configuration is more preferable for floorplan 

a) double BACK  + channel width spacing 

b) without double back + channel width spacing 

c) double back + row alignment

d) none of the above 

25. Concept of fixing time violations by adjusting clock arrival times at the registers in the preCTS stage is called 

a) time borrowing 

b) managing skew 

c) maintaining timing 

d) none of the above 

26. While calculating standard cell utilization what are all will be considered 

a) macro + blockage + standard cell (area)

b) macro + blockage (area)

c) macro + physical cells + standard cells (area)

d) all of the above 

27. RV checks Are needed for 

28. Inputs for LVS

a) spice + netlist + rule deck

b) spice + rule deck + lib files 

c) OASIS + netlist + lib 

d) none of the above 

29. Via3 will connect which of the following metal layers 

a) 1 and 3

b) 2 and 3

c) 3 and 4

d) none 

 

30.  A 4-bit modulo 16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50 ns. The max. clock frequency that can be used is equal to

31. A pulse has a period of 15 ms. Its frequency is

32. A 8-bit successive approximation ADC has a full-scale reading of 2.55 volts and its conversion time for an analog input of 1 volt is 20 µs. The conversion time for a 2 volts input will be?

33 . How many binary numbers are required to represent a decimal number 748?

 34. DRC is used to 

a)to ensure chip fabrication

b)to ensure chip doesn't get heated 

c)to verify parasitics on chip

d) all of these 

35.  Antenna diodes are used for 

a) to protect the gate 

b) protect VDD and VSS

c) to protect the substrate 

d) all of the above

36.  Buffers are added to 

a) to fix timing violations 

b) to fix DRC

c) to fix parasitic values 

d) all 

37. Metal pitch and metal spacing are the same 

True

False

38. What is the effect of high drive strength buffer when added in the long net 

a) delay of net decreases

b) delay of net increases 

c) delay doesn't effect 

d) none of the above 

39. Cross talk glitch leads to 

a)timing failure 

b) functional failure 

c) substrate failure 

d)all of these 

40. Programmable special cells used during ECO

a) gate array filler cells

b) filler cells

c) metal fills 

d)decap cells 

41. What is a physical cell?

a) cell which doesn't have any functionality 

b)  cell is not synthesized 

c) cell which is inserted only in layout 

d) all of the above 

42. Power gating technique in low power is used to reduce 

a)static power 

b)leakage power 

c)internal power 

d) all of the above 

43. Which of the following is not present in SDC 

a) max cap

b) max trans 

c) max current density 

d) max fanout 

44. The phenomenon associated with transistor switching when the gate voltage may appear less than the local ground potential 

a) ground bounce 

b) supply bounce

c) glitch 

D) none 

45. Leakage recovery can be achieved through 

a)Hvt to Svt

b) Lvt to Hvt

C)Rvt to Lvt.

d) svt to lvt

46. Which of the following must be fixed during physical design 

a) floating inputs 

b) floating outputs 

C) floating metals 

d) both b and c 

47. Which slew value will be propagated to slew _out of slew _A is 100 ps and slew_B is 80ps for hold analysis 

a) 80 ps

b) 100 ps

c) 20 pls

d) 180 ps

48. A 16-bit modulo 16 ripple counter uses JK flops if propagation delay is 25 ns, the max frequency of the clock is 

a) 25

b) 10

c) 2

d) 16

49. Digital signals transmitted on a single conductor must be transmitted in 

a) serial 

b) digital 

C) slow speed 

d) none 

50. In a certain digital waveform, the period is four times the pulse width, the duty cycle of the waveform will be? 

51. Follow pin connections to the standard s are done in encounter through

a)z- route 

b)s-route 

c)trail route 

d) nano- route 

52.set Y[ ]; 

set Z[a,b,c]; 

lappend $Y,$Z;

What is the output 

a) empty list 

b) [a b]

c) [a b c]

d) none

[ Note: If you find any question has typo error or wrong, comment for the correction.]

 Thank you.

Synthesis and Physical Design Interview Questions: Question Set -5

Code: CYPR2Y102020PD

Introduction and Experiences

1. Self Introduction
2. Explain about the projects that you have worked on. (Type of work and tools used)

Synthesis

1. Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages)
2. Explain about Synthesis Inputs. 
3. Differentiate between Logical and Physical Synthesis. (QoR impact between them)
4. Wire load model(WLM), Mode, Types of trees
5. Delay Calculation in WLM method. (Fanout based delay calculation)

 

Place and Route

1. What are Inputs for PnR and Initial Checks need to be done?
2. How to check for uniqueness of Netlist?
3. Explain stages in PnR.
4. Explain about useful skew and how it impacts the design.
5. How do we achieve a better insertion delay?
6. Explain about the CTS issues that you solved.
7. Explain Physical Cells at the transistor level.
8. Explain UPF, power domains, supply sets, isolation cells, retention registers.
9. Feedthru insertion procedure and minimizing them. How you did Partitioning and improved partition related size, ports creation, Congestion.

RTL

1. RTL Code for synchronous rst and asynchronous rst. (How do we write always block for this?)
2. How do you write RTL code for FSM? (Explain about the number of always blocks required and significance of each one)
3. Write RTL code for the traffic light system.

SignOff

1. Explain about the LEC procedure and issues faced and solved with respect to non-equivalent points.
2. How do we fix Setup and Hold time violations?
3. Explain about Dynamic and Leakage Power Consumption and methods to reduce them.
4. If the chip is fabricated and hold violation exists. So what will you do? (other than saying that chip won't work)
5. Scripting related to finding empty modules, Unix commands.

Post Credit: 

These questions are shared by one of our active group members. Thanks a lot for your contribution!!!

Physical Verification Interview Questions : Question set - 4

 

Code: QLCM2Y062020PV

General Questions

1. What are lambda based design rules?
2. What is nm in 10nm technology node?
3. Do you know about under bum density?
4. Any prior experience of PnR?
5. How do you import design in PnR?
6. Why ID layers have been given in lower nodes (10nm)?
7. Why nwell continuity is required?
8. Have you done scripting?
9. Can you write an algorithm?
10. What is drive strength?
11. Why the industry is moving towards lower technology nodes like 7nm or 5nm?
12. What are challenges seen in lower technology node?

Physical Only Cell

1. What is a tap cell?
2. What are the uses of tap cells?
3. What is Endcap or boundary cell?
4. How does halo cell avoid DRCs t boundary? What is there inside the halo cell that prevents DRCs ? How it is different from standard cells?
5. What difference it makes when you add halo cell in boundary instead of standard cell?
6. Why is the standard cell nwell bigger in size and slightly coming out of the standard cell? It is not so in halo cell.
7. Suppose a tap cell is covering 10um distance, then where should the next tap cell be placed in the same row?
8. How do you calculate the distance between tap cells in a row?

DRC

1. What kind of base DRCs have you encountered?
2. Have you seen DRCs between the standard cell and filler cell of the same height?
3. What is Endcap or boundary cell?
4. How did you solve DPT (double patterning)?
5. What metal DRC have you encountered?
6. What kind of via DRCs have you come across?
7. What will happen if GDSII has DRC unfixed and sent to Fab?
8. Is there any problem if the ID layers are interchanged?
9. Which ID layer is manufactured first?

LVS

1. Have you analyzed the LVS result or someone else analyzed the result and you fixed?
2. Apart from short and opens what errors have you seen in LVS and How did you resolve?
3. What kind of issues are seen in LVS?
4. What is priority errors in LVS? Could there be false violations?
5. Where does the tool start to calculate LVS from?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks, Karthik for sharing and helping people.

6.

11

Physical Verification Interview Questions : Question set - 3

 

Code: INTL2Y052020PV

Floorplan

1. What are the inputs for floorplan?
2. In order to make sure integration is DRC clean, what rules or guidelines need to be followed at the floorplan stage?
3. Can we abut macros on par boundary?
4. How will judge the congestion between two IPs during floorplan stage without actual routing being done?
5. Apart from IP alignment, what analysis have you done?
6. What do you check at the placement stage? 

Physical Only Cell

1. What are the types of physical only cells in the design?
2. In what stage are physical only cells placed in the design?
3. Why are different types of physical only cells needed in design?

Latch-up

1. Are you aware of latch-up in CMOS, can you elaborate?
2. Explain how the parasitics are formed?

Antenna Effect

1. What is the antenna effect?
2. How can antenna effect be solved?
3. Why metal jogging is done in the higher layer during antenna fixing?
4. Which diode is used as an antenna diode?
5. What parameters are considered while choosing the cutoff voltage of an antenna diode?
6. How do you decide the number of diodes that needs to inserted for the failing net?
7. On what basis have you inserted diodes?
8. If M12 is the highest metal in the design and it has antenna, how do you fix it?
9. Have you heard of nwell antenna?
10. Can power net have an antenna effect?
11. Can the antenna diode be placed in a different power from that of the affected cell?
12. What is the impact of placing the antenna diode on timing?
13. Where are the antenna diode terminals being connected?
14. Voltage or current that is causing the antenna effect?
15. How the gate area can be increased in antenna affected cell?
16. How are you adding the antenna in antenna affected cell?
17. What is the drive strength?
18. What is the W/L ratio?
19. Which layers are most susceptible to antenna violations, higher or lower layers? 
20. How do you handle antenna in clock net?

ECO Implementation

1. What are types of ECOs?
2. Where the ECOs generated and given to you or you prepared ECOs?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks Karthik for sharing and helping people.

Physical Verification Interview Questions : Question set - 2

Code: INTL2Y052020PV

General

1. What is done to solve congestion in lower and higher metal?
2. How cell spreading helps in routing congestion?
3. Cell spreading is done on what basis?
4. What is DFM and why is it needed?
5. What happens if DFM is not met?
6. What are the inputs to GDSII file?
7. What is crosstalk, Which checker is used to detect the crosstalk?
8. What is the difference between gate level netlist and layout netlist?
9. How does a MOSFET work?
10. What does the length of channel refer to?
11. Explain transfer characteristics of a CMOS Inverter.

DFM

1. Why Density needs to be maintained?
2. What kind of densities are there?
3. How do you know the density of each cell?
4. If there are 100 plus density windows, then how to fix it?
5. What happens if there are min or max density during fabrication?
6. Whats are the projects you have done related to synthesis and Physical Design?

DRC

1. What is DRC?
2. Will the design be clean if halos are places properly in design?
3. What are the types of DRC?

LVS

1. What is LVS What it checks for?
2. What are the inputs and outputs of LVS?
3. What are hierarchical shorts?
4. What are the inputs to generate the OASIS file?
5. What is the full form of OASIS?
6. What is the difference between ICC LVS and ICV LVS?
7. In what format does the tool calculate the LVS?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks Karthik for sharing and helping people.

Logic Synthesis and Physical Design Interview Questions : Question set - 1

 

Code: MDTK3Y062019PDSYN

1. Formal Introduction
2. Whats are the projects you have done related to synthesis and Physical Design?
3. Have you gone through Physical Design flow?
4. What is synthesis?
5. Whats are the inputs required for synthesis?
6. What does constraint files contain?
7.  What is a multicycle path?
8. What is a false path?
9. Why do we perform STA?
10. What is CTS?
11. Why do we perform Setup analysis?
12. How to fix setup violations?
13. What are the ways to fix the setup violations?
14. What is the clock skew?
15. Why CTS is done before Routing?
16. What is On-Chip Variation?
17. What is Antenna Effect?
18. What is library setup and hold time for a flip flop?
19. Why there is a setup time requirements for a flip flop?
20. Why Hold time required for a flip flop?
21. What is the temperature Inversion?
22. How does the threshold voltage vary with temperature?
23. How does mobility vary with temperature?
24. Do you have any questions for me?

Basic Dos and Don'ts for Freshers in VLSI Interview

Hello Guys,

As you all know that the entry in the VLSI Industry is not easy for freshers, and it becomes more difficult especially if you don't belong from tier-1 institutes of India. But keep good hopes always with you, people who are eligible, definitely get chance. So here important thing which I want to tell you is If you get an interview call, convert this rare opportunity into the offer later. And for freshers, believe me, what matters most is to start the first job irrespective of a big or small company. Once you are in the industry and working well, you can switch any company later. 

So, here are some Dos and Don'ts which a fresher's must follow during the interview. Never take too much pressure on the interview, but at the same time don't be ignorant. Your result will be determined on the basis of what you answer in the interview not what you know and understand. So being presentable and prepared matters most. 

Dos:

1. Choose the best environment:

If the interview is telephonic, you must choose a place where the network of your mobile is good, avoid any surrounding noise and use the best quality earphone. In a telephonic interview, your audio quality is a very important factor during the call. In case of the video call, make sure for the good bandwidth and audio/microphone connectivity and join the virtual meeting room on time. 

2. Be honest with your CV:

In fresher's interview, interviewers generally ask a few questions related to your CV only. So you must be aware whatever you have written in your CV and proper justification should be there if any questions arise from your CV. Be prepared and honest with your answers.

3. Think before answer:

Listen to the interviewer very carefully, take a small pause before answering if required and then answer. Many time your next question will come based on your current answer, so try to drive the interviewer in the right direction. 

4. Keep Answers short

Always try to keep your answer shorts, more you elaborate, more chances of mistakes. And some time interviewers are not interested to listen to the thing which he has not asked.

5. Answer to the point only

Always try to give the answer to the point. If you are not aware of the question, It's better to say Sorry and move to the next question instead of irrelevant answers. 

6. Be specific

If any question comes from your project/thesis be very specific, and tell them the exact problem/issue and how you solved that instead of giving a long theoretical answer. In the interview, your practical experience matters most than the general approach. But If any question comes to test your theoretical understanding then you may use a general concept for the explanation.

Don'ts:

1. Never rush to answer:

Sometimes a very well known question comes for which candidate is well prepared, so they start answering even before the interviewer complete the question. Avoid this thing, and wait for the completion of question. There may be some twist in the last part of the question.

2. Avoid criticism:

Sometimes questions come, like why do you want to join/work in a particular area, then never criticise the other domain, Just show your interest for which you have appeared in the interview 

3. Avoid exaggeration:

Never exaggerate any topic while answering a question, the best way is keep your answer short and to the point only.

Thank you!