Code: ALTRN0Y112020PD
Some companies take a written test sometimes to shortlist the candidates before the interview process. This is a common process if the applicants are large in numbers. In such written test, the format is MCQ and some short questions.
We are very thankful to one of our follower who has appeared in this test and shared these questions based on memory. The purpose of sharing this question is only to provide the right guidance to the candidate who is going to appear in such a written test. I would encourage all the freshers to practice these question for their future test/Interview. I would also encourage to find the answer to these question either by own. There is no sense of proving the answer to these questions here. But if someone finds any question really difficult to solve and open discussion in the comment section.
1. Hold slack equation
a) half cycle pathb) single cycle pathC) multicycle pathd) it never depends
a) max launch path delay and min capture path delayb) min launch path delay and max capture path delayc) max launch and capture path delayd) min launch and capture path delay
a) decreasing the space between metal layersb) decreasing strapsc) increasing drive strength of the driverd) increasing space between metal layers
a) to maintain well continuityb) to prevent latch upc) to prevent DRC'sd) all of the above
a) to ensure etching properlyb) to ensure density issuesc) to increase the area of the chipd)to ensure well continuity
a) opensb) shortsc) ERCd) all of the above
a) setup violationb) hold violationc) DRcsd) all of the above
a) trueb) falsec) based on SDCd) based on clock frequency
a) trueb) false
a) static stateb) when coolingc) when warmingd) all of the above
a) ratio of required layers and available layersb) ratio of available and requiredc) depending on availability of metalayersd) none of the above
a) doping concentrationb)distance between source and drainc) temperatured) all of the above
a) isolation cellsb) retention cellsc) level shiftersd) all
a) double BACK + channel width spacingb) without double back + channel width spacingc) double back + row alignmentd) none of the above
a) time borrowingb) managing skewc) maintaining timingd) none of the above
a) macro + blockage + standard cell (area)b) macro + blockage (area)c) macro + physical cells + standard cells (area)d) all of the above
a) spice + netlist + rule deckb) spice + rule deck + lib filesc) OASIS + netlist + libd) none of the above
a) 1 and 3b) 2 and 3c) 3 and 4d) none
a)to ensure chip fabricationb)to ensure chip doesn't get heatedc)to verify parasitics on chipd) all of these
a) to protect the gateb) protect VDD and VSSc) to protect the substrated) all of the above
a) to fix timing violationsb) to fix DRCc) to fix parasitic valuesd) all
TrueFalse
a) delay of net decreasesb) delay of net increasesc) delay doesn't effectd) none of the above
a)timing failureb) functional failurec) substrate failured)all of these
a) gate array filler cellsb) filler cellsc) metal fillsd)decap cells
a) cell which doesn't have any functionalityb) cell is not synthesizedc) cell which is inserted only in layoutd) all of the above
a)static powerb)leakage powerc)internal powerd) all of the above
a) max capb) max transc) max current densityd) max fanout
a) ground bounceb) supply bouncec) glitchD) none
a)Hvt to Svtb) Lvt to HvtC)Rvt to Lvt.d) svt to lvt
a) floating inputsb) floating outputsC) floating metalsd) both b and c
a) 80 psb) 100 psc) 20 plsd) 180 ps
a) 25b) 10c) 2d) 16
a) serialb) digitalC) slow speedd) none
a)z- routeb)s-routec)trail routed) nano- route
a) empty listb) [a b]c) [a b c]d) none
[ Note: If you find any question has typo error or wrong, comment for the correction.]
Thank you.
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