Physical Design Interview Questions for 3 years experience , Question set - 8

Code: EXIM4Y062021PD

Experience level : 3 years

1. Brief Introduction and major projects?
2. Tell me the most challenging part of your recent project
3. How does the lockup latch help to fix hold violations?
4. If we add a lockup latch, it might violate the setup? How will we fix it further?
5. How did you fix SigEM? What are patch wires?
6. What CTS constraints have you used?
7. How did you fix the setup violation?
8. Apart from setup and hold, what other checks do we perform in timing signoff?
9. What are the PV checks?
10. What are the sanity checks we do before starting PnR?




11. What are the reports of synthesis we check before PnR?
12. What are the physical cells we have used in PD and what are the uses of all those?
13. What is the latch-up issue and how well tap cells prevent latchup?
14. What is the endCap cell and what is the purpose of using that?
15. What is Dcap Cell and why do we use it?
16. What is the antenna effect?
17. What are the ways to fix the antenna effect?
18. How do antenna diodes help to fix the antenna violations?
19. If we have timing criticality and we can't use antenna diodes or floating gates, How can we fix the antenna?
20. If antenna violation is already the highest metal layer and we can use higher metal for metal hopping, how will fix the antenna?
21. How will you fix the antenna violations on via?
22. What is a metal cut layer?
23. What is the crosstalk delay?
24. What is the crosstalk noise?

Physical Design Interview Questions : Question set -7

 

Code: CDN5Y062021PD

Experience level: 5 Years

For Application Engineer

1. What are the major differences between 7nm and 12/14nm technology nodes?
2. What are the new DRC rules in the 7nm technology node?
3. What is the via-piller?
4. What is double patterning?
5. How many layers have double patterning in the 7nm node?
6. How tool performs placement steps?
7. Why do we perform scan chain reordering?
8. What is scan mode, why do we need that?
9. What is ECF (Early Clock Flow) flow?
10. What are the benefits of ECF flow?




11. Can you explain the CTS flow?
12. What are the low power techniques used in data and clock paths?
13. Where does the clock-gater use?
14. Have you built a custom clock tree?
15. What are the constraints you have given to the clock tree?
16. How did you solve max_trans violations in the clock path?
17. How to provide different clock tap points in H-Tree?
18. How many clocks were there in your block?
19. How were they related?
20. How did you analyze the clock domain crossing paths?
21. What is a lock-up latch and how does it helps in hold fixing?
22. What was the target skew in your block?
23. What value of skew you achieved?

Interview questions asked for DFT Engineer (Fresher) - Question Set - 07

 

Code: INTL0Y032021DFT

This interview was held for the position of DFT Engineer with 0 years of experience. I personally felt the questions are good and generic which will help the freshers in other domains too.

Round-1:

1) Differences between MOSFET and FINFET ?
2) Puzzle:  A blind man walking in a desert has 2 red pills and 2 blue pills with him. He has to take one red pill and one blue pill each per day. How can he do that correctly?
3) Limitations of MOSFET
4) Puzzle: If a man climbs 15 m well. He climbs 4 m every day and slips 3 m . How many days it takes for him to get outside of the well?
5) What is set up time and hold time?
6) What is set up time and hold time violations?

7) What is metastability and do you know its physical significance?
8) What is a critical path?
9) How can you improve the timing?
10) How can you fix the setup time violations?
11) Implement a 2:1 mux for AND gate?
12) Draw the timing diagram of half adder?
13) What is blocking and non-blocking assignments?

14) What is synchronous and Asynchronous reset?

15) Why do we need DFT and what do you mean by that ?
16) Explain briefly the methods of DFT?
17) Why do you need to make flip flops initialized in an ad hoc technique?
18) What are controllability and observability?
19) If you fabricate a full adder and do the functional test and verify outputs are correct, then do you still require DFT also?
20) What is BIST?
21) What is JTAG?
22) Difference between verification and DFT?
23) What is yield?
24) Explain your course works and the projects.
25) Difference between RAM, ROM.
26) What is DMA?

Round-2:

1) Short channel effects in MOSFET.
2) Brief about JTAG.
3) Any insight into BSDL.
4) What are the different faults that occur while fabrication?
5) What is bridging fault?
6) What is fault collapsing?
7) Draw a D-flipflop along with a timing diagram.
8) What is Stuck at faults?

9) What do you mean by clock skew?
10) Is Hold time dependent on clock frequency?
11) Is clock skew an advantage or not?
12) Current technology node used in industry?
13) Is set up time-dependent on clock frequency?
14) Why do you need a reset in flip flop?
15) What is the multicycle path?
16) Any tools for DFT?

17) Why DFT is in the front end?
18) VLSI design flow.
19) OR gate using 2:1 mux
20) How to do if statement synthesis?
21) How do a case statement in Verilog synthesis?
22) What is Inferred latch?
23) List out a few Power optimization methods in STA.

My sincere thanks to the teamVLSI member who shared this genuine question set with us. If you feel such questions help you in your interview preparation, You are encouraged to share your interview questions with us at teamvlsi2014@gmail.com and help the community as you are getting help.

Synthesis and Physical Design Interview Questions: Question Set -5

Code: CYPR2Y102020PD

Introduction and Experiences

1. Self Introduction
2. Explain about the projects that you have worked on. (Type of work and tools used)

Synthesis

1. Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages)
2. Explain about Synthesis Inputs. 
3. Differentiate between Logical and Physical Synthesis. (QoR impact between them)
4. Wire load model(WLM), Mode, Types of trees
5. Delay Calculation in WLM method. (Fanout based delay calculation)

 

Place and Route

1. What are Inputs for PnR and Initial Checks need to be done?
2. How to check for uniqueness of Netlist?
3. Explain stages in PnR.
4. Explain about useful skew and how it impacts the design.
5. How do we achieve a better insertion delay?
6. Explain about the CTS issues that you solved.
7. Explain Physical Cells at the transistor level.
8. Explain UPF, power domains, supply sets, isolation cells, retention registers.
9. Feedthru insertion procedure and minimizing them. How you did Partitioning and improved partition related size, ports creation, Congestion.

RTL

1. RTL Code for synchronous rst and asynchronous rst. (How do we write always block for this?)
2. How do you write RTL code for FSM? (Explain about the number of always blocks required and significance of each one)
3. Write RTL code for the traffic light system.

SignOff

1. Explain about the LEC procedure and issues faced and solved with respect to non-equivalent points.
2. How do we fix Setup and Hold time violations?
3. Explain about Dynamic and Leakage Power Consumption and methods to reduce them.
4. If the chip is fabricated and hold violation exists. So what will you do? (other than saying that chip won't work)
5. Scripting related to finding empty modules, Unix commands.

Post Credit: 

These questions are shared by one of our active group members. Thanks a lot for your contribution!!!

Physical Verification Interview Questions : Question set - 4

 

Code: QLCM2Y062020PV

General Questions

1. What are lambda based design rules?
2. What is nm in 10nm technology node?
3. Do you know about under bum density?
4. Any prior experience of PnR?
5. How do you import design in PnR?
6. Why ID layers have been given in lower nodes (10nm)?
7. Why nwell continuity is required?
8. Have you done scripting?
9. Can you write an algorithm?
10. What is drive strength?
11. Why the industry is moving towards lower technology nodes like 7nm or 5nm?
12. What are challenges seen in lower technology node?

Physical Only Cell

1. What is a tap cell?
2. What are the uses of tap cells?
3. What is Endcap or boundary cell?
4. How does halo cell avoid DRCs t boundary? What is there inside the halo cell that prevents DRCs ? How it is different from standard cells?
5. What difference it makes when you add halo cell in boundary instead of standard cell?
6. Why is the standard cell nwell bigger in size and slightly coming out of the standard cell? It is not so in halo cell.
7. Suppose a tap cell is covering 10um distance, then where should the next tap cell be placed in the same row?
8. How do you calculate the distance between tap cells in a row?

DRC

1. What kind of base DRCs have you encountered?
2. Have you seen DRCs between the standard cell and filler cell of the same height?
3. What is Endcap or boundary cell?
4. How did you solve DPT (double patterning)?
5. What metal DRC have you encountered?
6. What kind of via DRCs have you come across?
7. What will happen if GDSII has DRC unfixed and sent to Fab?
8. Is there any problem if the ID layers are interchanged?
9. Which ID layer is manufactured first?

LVS

1. Have you analyzed the LVS result or someone else analyzed the result and you fixed?
2. Apart from short and opens what errors have you seen in LVS and How did you resolve?
3. What kind of issues are seen in LVS?
4. What is priority errors in LVS? Could there be false violations?
5. Where does the tool start to calculate LVS from?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks, Karthik for sharing and helping people.

6.

11

Physical Verification Interview Questions : Question set - 3

 

Code: INTL2Y052020PV

Floorplan

1. What are the inputs for floorplan?
2. In order to make sure integration is DRC clean, what rules or guidelines need to be followed at the floorplan stage?
3. Can we abut macros on par boundary?
4. How will judge the congestion between two IPs during floorplan stage without actual routing being done?
5. Apart from IP alignment, what analysis have you done?
6. What do you check at the placement stage? 

Physical Only Cell

1. What are the types of physical only cells in the design?
2. In what stage are physical only cells placed in the design?
3. Why are different types of physical only cells needed in design?

Latch-up

1. Are you aware of latch-up in CMOS, can you elaborate?
2. Explain how the parasitics are formed?

Antenna Effect

1. What is the antenna effect?
2. How can antenna effect be solved?
3. Why metal jogging is done in the higher layer during antenna fixing?
4. Which diode is used as an antenna diode?
5. What parameters are considered while choosing the cutoff voltage of an antenna diode?
6. How do you decide the number of diodes that needs to inserted for the failing net?
7. On what basis have you inserted diodes?
8. If M12 is the highest metal in the design and it has antenna, how do you fix it?
9. Have you heard of nwell antenna?
10. Can power net have an antenna effect?
11. Can the antenna diode be placed in a different power from that of the affected cell?
12. What is the impact of placing the antenna diode on timing?
13. Where are the antenna diode terminals being connected?
14. Voltage or current that is causing the antenna effect?
15. How the gate area can be increased in antenna affected cell?
16. How are you adding the antenna in antenna affected cell?
17. What is the drive strength?
18. What is the W/L ratio?
19. Which layers are most susceptible to antenna violations, higher or lower layers? 
20. How do you handle antenna in clock net?

ECO Implementation

1. What are types of ECOs?
2. Where the ECOs generated and given to you or you prepared ECOs?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks Karthik for sharing and helping people.

Basic Dos and Don'ts for Freshers in VLSI Interview

Hello Guys,

As you all know that the entry in the VLSI Industry is not easy for freshers, and it becomes more difficult especially if you don't belong from tier-1 institutes of India. But keep good hopes always with you, people who are eligible, definitely get chance. So here important thing which I want to tell you is If you get an interview call, convert this rare opportunity into the offer later. And for freshers, believe me, what matters most is to start the first job irrespective of a big or small company. Once you are in the industry and working well, you can switch any company later. 

So, here are some Dos and Don'ts which a fresher's must follow during the interview. Never take too much pressure on the interview, but at the same time don't be ignorant. Your result will be determined on the basis of what you answer in the interview not what you know and understand. So being presentable and prepared matters most. 

Dos:

1. Choose the best environment:

If the interview is telephonic, you must choose a place where the network of your mobile is good, avoid any surrounding noise and use the best quality earphone. In a telephonic interview, your audio quality is a very important factor during the call. In case of the video call, make sure for the good bandwidth and audio/microphone connectivity and join the virtual meeting room on time. 

2. Be honest with your CV:

In fresher's interview, interviewers generally ask a few questions related to your CV only. So you must be aware whatever you have written in your CV and proper justification should be there if any questions arise from your CV. Be prepared and honest with your answers.

3. Think before answer:

Listen to the interviewer very carefully, take a small pause before answering if required and then answer. Many time your next question will come based on your current answer, so try to drive the interviewer in the right direction. 

4. Keep Answers short

Always try to keep your answer shorts, more you elaborate, more chances of mistakes. And some time interviewers are not interested to listen to the thing which he has not asked.

5. Answer to the point only

Always try to give the answer to the point. If you are not aware of the question, It's better to say Sorry and move to the next question instead of irrelevant answers. 

6. Be specific

If any question comes from your project/thesis be very specific, and tell them the exact problem/issue and how you solved that instead of giving a long theoretical answer. In the interview, your practical experience matters most than the general approach. But If any question comes to test your theoretical understanding then you may use a general concept for the explanation.

Don'ts:

1. Never rush to answer:

Sometimes a very well known question comes for which candidate is well prepared, so they start answering even before the interviewer complete the question. Avoid this thing, and wait for the completion of question. There may be some twist in the last part of the question.

2. Avoid criticism:

Sometimes questions come, like why do you want to join/work in a particular area, then never criticise the other domain, Just show your interest for which you have appeared in the interview 

3. Avoid exaggeration:

Never exaggerate any topic while answering a question, the best way is keep your answer short and to the point only.

Thank you!