Interview questions for experienced Physical Design Engineer, Question set - 9

 

Code: CDN4Y072021PD

Experience level: 4 Year

Profile: Physical Design Engineer

1. Introduction and physical design experience

2. What major differences have you observed in the 7nm and 14nm process nodes?

3. What is the functionality of this circuit? (He drawn schematic in paint)

4. Do you think, is there any issue with the above circuit? If so what would you suggest for improvement?

5. When clock gatting circuit has added in the design RTL/Synthesis/PnR?

6. What are the checks you perform before starting the floorplan?

7. What is a library check?

8. What are the information available inside the .lib file?

9. How is the timing of a cell defined in .lib file?

10. What if the .lib file is missing but .lef file is available for a cell? and similarly, if .lef file is missing but .lib file is present for a cell?

11. How do we define the core area for any block?

12. How do we decide the height and width of a block?

13. What are the guidelines we need to follow in macro placement?

14. Is there any rule for abutting the macros?

15. What steps exactly tool does in the placement stage?

16. Why do we use boundary cells?

17. Why can't we use placement blockage at the end of each row in place on the boundary cell?

18. What was the target latency in your block and what has been achieved?

19. Can you explain the ccopt method?

20. Which flavour of Vt cell you used in the clock tree?

21. Which type of derating you have been used in your different projects?

22. Why do we start using POCV when we had AOCV derate?

23. What is the shielding of a net? How it works?

24. Have you used shielding in your block?

25. What is NDR?

26. What is the difference between shielding and NDR? Can we use only one of these two?

27. Where did you placed the clock gating cell, near the sink or source?

28. Can you tell me the advantage and disadvantages of placing ICG near the sink and near the source?

29. What is CPPR?

30. (A diagram has been drawn in paint as shown below) In this diagram can you tell me between which edges the setup and hold timing will be checked?

31. If we change the scenario like below, Now between which edge setup and hold will be checked? 

32. What is internal power and switching power?

33. What is the impact of the threshold voltage of a cell on the internal power and switching power?

34. What is the impact of IR drop in cell delay?

35. How do you fix the static IR drop?

36. What was the limit of dynamic IR drop in your recent project?

Physical Design Interview Questions for 3 years experience , Question set - 8

Code: EXIM4Y062021PD

Experience level : 3 years

1. Brief Introduction and major projects?
2. Tell me the most challenging part of your recent project
3. How does the lockup latch help to fix hold violations?
4. If we add a lockup latch, it might violate the setup? How will we fix it further?
5. How did you fix SigEM? What are patch wires?
6. What CTS constraints have you used?
7. How did you fix the setup violation?
8. Apart from setup and hold, what other checks do we perform in timing signoff?
9. What are the PV checks?
10. What are the sanity checks we do before starting PnR?




11. What are the reports of synthesis we check before PnR?
12. What are the physical cells we have used in PD and what are the uses of all those?
13. What is the latch-up issue and how well tap cells prevent latchup?
14. What is the endCap cell and what is the purpose of using that?
15. What is Dcap Cell and why do we use it?
16. What is the antenna effect?
17. What are the ways to fix the antenna effect?
18. How do antenna diodes help to fix the antenna violations?
19. If we have timing criticality and we can't use antenna diodes or floating gates, How can we fix the antenna?
20. If antenna violation is already the highest metal layer and we can use higher metal for metal hopping, how will fix the antenna?
21. How will you fix the antenna violations on via?
22. What is a metal cut layer?
23. What is the crosstalk delay?
24. What is the crosstalk noise?

Synthesis and Physical Design Interview Questions: Question Set -5

Code: CYPR2Y102020PD

Introduction and Experiences

1. Self Introduction
2. Explain about the projects that you have worked on. (Type of work and tools used)

Synthesis

1. Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages)
2. Explain about Synthesis Inputs. 
3. Differentiate between Logical and Physical Synthesis. (QoR impact between them)
4. Wire load model(WLM), Mode, Types of trees
5. Delay Calculation in WLM method. (Fanout based delay calculation)

 

Place and Route

1. What are Inputs for PnR and Initial Checks need to be done?
2. How to check for uniqueness of Netlist?
3. Explain stages in PnR.
4. Explain about useful skew and how it impacts the design.
5. How do we achieve a better insertion delay?
6. Explain about the CTS issues that you solved.
7. Explain Physical Cells at the transistor level.
8. Explain UPF, power domains, supply sets, isolation cells, retention registers.
9. Feedthru insertion procedure and minimizing them. How you did Partitioning and improved partition related size, ports creation, Congestion.

RTL

1. RTL Code for synchronous rst and asynchronous rst. (How do we write always block for this?)
2. How do you write RTL code for FSM? (Explain about the number of always blocks required and significance of each one)
3. Write RTL code for the traffic light system.

SignOff

1. Explain about the LEC procedure and issues faced and solved with respect to non-equivalent points.
2. How do we fix Setup and Hold time violations?
3. Explain about Dynamic and Leakage Power Consumption and methods to reduce them.
4. If the chip is fabricated and hold violation exists. So what will you do? (other than saying that chip won't work)
5. Scripting related to finding empty modules, Unix commands.

Post Credit: 

These questions are shared by one of our active group members. Thanks a lot for your contribution!!!

Logic Synthesis and Physical Design Interview Questions : Question set - 1

 

Code: MDTK3Y062019PDSYN

1. Formal Introduction
2. Whats are the projects you have done related to synthesis and Physical Design?
3. Have you gone through Physical Design flow?
4. What is synthesis?
5. Whats are the inputs required for synthesis?
6. What does constraint files contain?
7.  What is a multicycle path?
8. What is a false path?
9. Why do we perform STA?
10. What is CTS?
11. Why do we perform Setup analysis?
12. How to fix setup violations?
13. What are the ways to fix the setup violations?
14. What is the clock skew?
15. Why CTS is done before Routing?
16. What is On-Chip Variation?
17. What is Antenna Effect?
18. What is library setup and hold time for a flip flop?
19. Why there is a setup time requirements for a flip flop?
20. Why Hold time required for a flip flop?
21. What is the temperature Inversion?
22. How does the threshold voltage vary with temperature?
23. How does mobility vary with temperature?
24. Do you have any questions for me?