Placement Steps in Physical Design

Placement is a very important stage of physical design where all the standard cells get placed inside the core boundary. Overall QoR of the design greatly depends on the fact that how well placement is done. You must have noticed that the placement stage takes quite a large runtime. Actually, the tool performs various steps in a sequence to complete the placement stage. In this article, we will try to understand what are the important steps and the order in which the EDA tools perform to complete the placement stage.

Placement is the process of placing the standard cells inside the core boundary in an optimal location. The tool tries to place the standard cell in such a way that the design should have minimal congestions and the best timing. Every PnR tool provides various commands/switches so that users can optimize the design in a better way in terms of timing, congestion, area, and power as per their requirements. Based on the preferences set by the user, the tool tray to place and optimize it for better QoR. Placement does not place only the standard cells present in the synthesized netlist but also places many physical only cells and adds buffers/inverters as per the requirement to meet the timings, DRV, and foundry requirements. Here are the basic steps which the tool performs during the placement and optimization stage.

placement steps:

1. Pre Placement
2. Initial Placement / Course Placement / Global Placement
3. Legalization
4. HFNS (Hign Fanout Net Synthesis)
5. Iteration for Congestion, Timing, DRV, and Power Optimization
6. Multibit flop conversion
7. Timing optimization iterations
8. Scan-Chain Reorder
9. Tie Cell insertion
10. Save Design

1. Pre Placement:

Figure-1: Pre-placement step

Before starting the actual placement of the standard cells present in the synthesized netlist, we need to place various physical only cells like end-cap cells, well-tap cells, IO buffers, antenna diodes, and spare cells. A typical view after preplacement has shown in figure-1. Why these cells are required to place and how do we place them has been discussed separately in this article. Here we will focus mainly on the placement steps of standard cells present in the synthesized netlist.

2. Initial Placement / Global Placement / Course Placement 

Figure-2: Global placement before legalization

Once the pre Placement stage has been completed, We can start the placement of standard cells but before that, we have to provide all the correct placement and optimization settings that we want to be applied while the tool does the placement and optimization. These settings could be like partial placement blockage or density screen setting, bound or region creation, cell/instance padding, path_groups and effort, enabling the early clock flow (ECF) in case of innovus, enabling the extreme flow, enabling the useful skew, global congestion effort, global timing effort, power effort, Multibit flop conversion and many more.

After providing all these placement settings we can call the placement command (place_opt_design in case of innovus). The tool first does the global placement in which the tool determines the approximate location of each cell according to the timing, congestion, and multi-voltage constraints (in the case of innovus Gigaplace engine is called in this step). Any pre-placed macros will work as a placement blockage. In this stage, the tool will not check any overlap of instances. A typical figure of global placement has shown in figure-2 where you can see that the standard cells are placed in an approximate location but without legalization. 

3. Legalization

In the global placement stage, the instances are left with overlap. In this step, the tool will move the instances in nearby places to overcome the overlap. To match the proper power pins like the vdd pin of a standard cell should be on the vdd rail and vss on vss rail and for that if the fliping of instance is required tool also do the flipping. This process is called legalization. After this step, every instance should be placed in a legal location and there should be no overlaps. This step is also called refine placement.

4. HFNS (Hign Fanout Net Synthesis)

Initially, there are some nets which have very high numbers of fanout. We have a constraint of maximum fanout, so we need to distribute the sinks on nets to different drivers. The process of adding buffers and splitting the fanout is called high fanout net synthesis (HFNS). So In this step, all high fanout nets get synthesized.

5. Iteration for Congestion, Timing, DRV, and Power Optimization

In this step tool first, do an early global route and estimate the routing overflow/congestions in the design. The tool tries to initially minimize the congestion in this stage. Next, the tool starts the RC extraction to calculate the delay for setup analysis. The tool tries to minimize the setup WNS and TNS in this step. Similarly, the tool also tries to minimize the DRV and Power in this stage.

6. Multibit flop conversion

If the user enables the multi-bit flip flop conversion in the flow then the tool will first check the available multibit flops in the library. (You can read more about multi-bit cell here) The tool considers the criticality of timing associated with a single bit of flop and the user constraint set for multi-bit conversion and based on the constraints the tool converts the single-bit flop into multibit flops.

7. Timing optimization iterations

This is a long step in which the tool tries to minimize the WNS and TNS of each path group in various iterations. There are several iterations required to get a minimum WNS and TNS depending upon the effort set and initial WNS number. In case the result is not good after this stage, we can further run incremental optimization for timing. Similarly, for congetion, we can run congestion repair followed by incremental optimization to get a better result. But these additional steps will increse the run time.

8. Scan-Chain Reorder

Figure-3: Scan Chain before placement

Scan chain stitching has been done arbitrarily in synthesis. After placement and optimization, we have a location for each scan flops so it needs to be reordered for better routability. The tool performs a reordering of the scan chain in this step which is good for both timing and congestions. 

Figure-4: Scan chain after placement

Figure-5: Scan Chain after Scan chain reodrder

 

9. Tie Cell insertion

There are some unused inputs of logic gates in the netlist which is tied to either vdd or vss. We can not leave any inputs of the standard cell as floating, it must be tied either vdd or vss. Connecting an input of logic cell that is the gate of a transistor directly to vdd or vss is not recommended and for that, we have tie high and tie low cells in the library. (You may watch this video on tie cells for more details). So In this step tool places tie high and tie low cells which is basically a single output logic cell, and it connects the input of the logic gate which needs to connect vdd or vss respectively. 

10. Save Design

Finally, we save the database and we will use this database in the next stage, that is in the clock tree synthesis.

Pre-placement Activities in Physical Design

 In a broader sense, PnR (Place and Route) stage in physical design is basically Placement and Routing of all the instances present in the netlist in a defined core area in such a way that it should meet design rules and timing requirements. But before starting the actual automatic placement of instances by the PnR tool, there are certain activities which must be done prior to placement and those are called pre-placement activities. In this article, we will discuss some important pre-placement activities. 

Pre-placement activities in PnR

Major pre-placement activities:

• Pin placement
• Macro placement 
• Halo and routing blockage 
• Power plan
• Boundary cell/End cap cell placement
• Well tap cell placement
• Partial placement blockage /Density screen creation

Here we will discuss these activities in details in order as they needed to be performed. 

Pin placement:

In block-level PnR, input-output pins location are generally decided by the full-chip owner and the pin def is given to block owners. But some times pin location are not fixed at the top level and meanwhile block owner need to place them as per their convenience.

PnR tools provide a pin editing utility in their tools through which large numbers of pins can be placed easily. For innovus we can open the pin editor as Edit --> Pin Editor

Basically, we need to provide the following inputs to pin editor and corresponding image is shown a  typical pin placement.

 

 Pin list 

Metal layer 

Pin width

Pin depth

Side/edge

Spread / Distance between two pins 

 

Pin placement in PnR

Pins location could be either on edge of core or inside the core also. In case of pin def is available, we just need to defIn the pin.def file. In Innovus we can defIn the pin def file as bellow.

defIn <pin.def> 

Once all pins are placed, we can check that. In innovus we have a command. 

checkPinAssignment

The above command will give the total number of pins, the number of legal/illegal pins, the number of placed/unplaced pins.

Sometimes some i/o pins might have short with the PG structure, We can verify those shorts using following innovus command.

verify_PG_short -no_routing_blkg -no_cell_blkg

In case there are some shorts, we can fix those using following innovus command.

editPin -pin <pin name> -fixOverlap

Once all the pins are placed, we can defOut pins in a file for future use.

selectPin *    ;  Or   selectPin [dbGet top.terms]

defOut -selected <file_name>

Macro Placement:

Macro placement is a major step of the floorplan and the QoR (quality of result) of PnR is strongly dependent on the macro placement. A good macro placement requires thorough analysis of data flow in the block.
A bad floorplan could result in congestion and bad internal timings. There are some steps which must be followed especially in a macro dominating block. A detail discussion on macro placement strategy is explained in this article (will be linked soon).

Halo and Routing blockage:

Macros having high pins count near the edges generally and if the standard cell placement is high there, it could lead congestion. To avaoid this congestion we neet to put halo around the macro. (Halo is explained here - will be linked soon). The macro design needs more metal layers than normal standard cell and its pins are available in higher metal layers than the standard cells. So we need to put routing blockage for the layers which are used inside the macro. The power rails are blocked over the macros and power is delivered to the macros directly from power stripes.

Power Plan:

A power plan is a very robust power grid structure to deliver power to all macros and standard cells available in the design without much IR drop in the power grid. power grid takes power from bumps on the top metal layer and it delivers power to the lowest maetal layer in which standard cells follow pin available. 

From bumps, power goes to power stripe and power stripe delivers power to the VDD and VSS rails. Macros get power directly from power stripe as in place of macro there are no power rails drawn. 

Boundary cell placement:

Each placement row must be terminated with a boundary cell at both ends. Why we need boundary cells and what are the function of boundary cells, has been discussed in this article.

Well tap cell placement:

To get tap the psub to VSS and the nwell to VDD in order to avoid the latch-up issue in the design we need to place well tap cells at regular intervals in the core area. A detail discussion on well tap cells and its placement has been discussed in this article.

Partial placement blockage:

To avoid the congestion, we need to place partial placement blockage especially in the region where the pin density is more. We generally place partial placement blockage in the channel regions and the regions where io pins are placed. If the cell placement density will become high in this region, it may cause congestion as these areas already has lots of pin connections. 

Apart from these major activities, there are many other things which we need to on block specific like antenna cell placement, TCD Cells, PCLAMP cell placement. In the lower node, we need to check base DRC also after the macro placement steps. 

Thanks! 

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Sanity Checks before Floorplan in Physical Design

Sanity checks are an important step for physical design engineers to make sure that the inputs received for physical design are correct and consistent. Any issues in the input files may cause problems in the later stages. So it is important to perform the sanity checks in the initial stage that is when the design is loaded in PnR tool and before the start of the floorplan.

Here is a list of checks which must be performed before the floorplan of design.

Figure-1: Sanity checks before floorplan

Library Check:

In library check, basically, we validate the libraries before starting the physical design by checking the consistency between the physical and logical library.  It also checks the quality of both libraries and reports the error if any. The cells used in the design must be present in the logical as well as in the physical library.

Innovus commands:

checkDesign -physicalLibrary : This command will check the physical library and report that all the cells used in design have their LEF view or not.

checkDesign -timigLibrary : This command will check the timing library and report that all the cells used in design have defined in timing library or not.

checkDesign -all : This command will check the missing or inconsistent library and design data.

ICC command:

check_library : Performs consistency checks between the logical and physical library, across the logical library and within the physical library.

Netlist Check:

Netlist must be checked for consistency. This check analyzes the currently loaded netlist and reports the inconsistency if any. Netlist check mainly checks:

1. Floating input pins and nets
2. No direct connection between VDD and VSS
3. Multidriven nets
4. combinational loops
5. Unloaded outputs
6. Uncontraints pins
7. Mismatch pin count between instance and reference

Innovus command:

checkDesign -netlist

ICC command:

check_design

SDC Check:

SDC file must be checked before start the design. Some of the common issues in SDC file are as follow.

1. Unconstrained path
2. Clock is reaching to all synchronous elements
3. Multiclock driven registers
4. Unconstrained endpoint
5. Input/output delay missing for a port
6. Slew or load constraint missing for a port
7. Missing clock definition

Innovus command:

check_timing

ICC command:

check_timing

Thank you.

ASIC Design Flow - An Overview

In this post, ASIC (Application Specific Integrated Circuit) Design flow has been explained. The very first step of ASIC flow is design specification, which comes from the customer end. Where customer writes down the specification of the chip basically the functionality which he wants to develop in a chip.  The whole design process is going through various design cycles and it generally takes 6 to 24 months to complete the design depending on the complexity inside the chip.
The complete ASIC design process can be divided into two parts.

1. Front End Design
2. Back End Design

Front End Design:

Front end design process starts with the specification received from the customer end. RTL (Register Transfer Level) design engineer converts the specification into an RTL code using the HDL (Hardware Description Language) generally either in Verilog or VHDL. Once the RTL code is written, RTL designer simulates the code in RTL Simulator and check the functionality of the design. Once the functionality of code is correct and verified by the verification engineers and if there is no bug found, This RTL code is taking to the next stage which is logic synthesis. This flow starts with RTL coding and ends with GDS (Graphic Data Stream)  file which is the final output of back end design, so this complete flow is also known as RTL to GDS (RTL2GDS) flow. A Simple flow diagram has been described here. 

Back End Design:

RTL code received from the front end engineer is technology independent, now the next step is Logic synthesis. 

Logic Synthesis:  In logic synthesis, a high-level description of the design (RTL Code) is converted into an optimized gate-level representation of a given standard cell library and certain design constraints. Now the code is in the form of a gate-level netlist of a particular standard cell library. LEC (Logic Equivalence Check is must in this stage to make sure that there are not logical changes occurred during the synthesis. During logical Synthesis, we also get various reports on timing power and area of design. We also get an SDC (Synopsys Design Constraint) file in this stage which is used in the next stage. DFT (Design For Testability) Insertion is also done in this stage to verify the chip after fabrication is done. 

Place and Route (PnR): Gate level netlist after DFT Insertion and SDC file is taken as input for the PnR and based on standard cells library, PnR starts. The goal of PnR stage is to place all the standard cells, Macros and I/O pads with minimal area, with minimal delay and Route them together in such a way that there is no DRC (Design Rule Check) error. The final output of this stage is the layout of design in the form of GDSII file which is defacto standard of layout file in the industry. 

PnR stage is a very challenging stage with large design cycle time depending on the complexity of a chip. This stage is further divided into various sub-stages. The main stages are starting from Design Import, followed by FloorPlan, Power Plan, Placement, CTS (Clock Tree Synthesis), and Routing. 

After routing we expect the design has met the timing and all DRC, But in the modern chip, it's not easy to close the design in this stage. So Further we go to Signoff stage.

Signoff: If there are some timing violations in post route design, we have a further stage called ECO (Engineering Change Order) where we can fix the timing violations. Apart from timing violation, there may be issues like IR Drop, DRC Violations all these are fixed in this stage and a final layout file free from all the violation is streamed out in GDSII format. This process is known as tapeout in ASIC flow. This is the final design stage and gdsII file is sent to fabrication lab for the fabrication of chip.

Thank you.