Inputs for Physical Design | Physical Design input files

In this article, we will discuss what are the inputs required to begin the physical design. In the previous article, we have discussed the physical design flow and sanity checks before the floorplan. Inputs required for physical design can be categories broadly into two types. Some inputs are mandatory in all the cases but some are required for a specific purpose. Figure-1 shows the list of inputs required for physical design and categories the mandatory and optional inputs.

Figure-1: Inputs for Physical Design

In the set input files, the first set is design-related files which contain Gate level netlist file and design constraint files. These files come from the synthesis team. Let's briefly see the content of these files.

Gate level netlist: 

This is the synthesized netlist. The synthesis team performs synthesis on RTL code with the standard cell libraries and constraints and converts the RTL code into the gate-level netlist based on available standard cells. This file contains all the instances of design and their connection. 

 

Constraint file: 

Constraint file is popularly known as SDC file by its extension of the file. It contains basically,

• Units (Time, Capacitance, Resistance, Voltage, Current, Power)
• System interface (Driving cell, load)
• Design rule constraints (max fanout, max transition)
• Timing constraints (Clock definitions, clock latency, clock uncertainty, input/output delay)
• Timing exceptions (Multi-cycle and false paths)

A detail description of SDC file is explained here

Now some inputs are required which are related to standard cell libraries. These files are provided by the standard cell library vendor and these files are as follow. 

Logical libraries: 

The logical library is also called a timing library or functional library or power library as it contains the functionality, time and power information of cells. This file contains basically the following information of the standard cells or macros. 

• Timing details of the standard cells / macros ( delay, transitions)
• Setup and hold time of  standard cells / macros
• Functionality details of  standard cells /macros
• Area of standard cells / macros
• Pin directions and capacitance
• Leakage power of standard cells / macros 

The logical libraries could be either in liberty format .lib file for Cadence tool or in the form of .db file for Synopsys tool. There are different logical files for different PVT corners. Liberty file is created by doing the standard cell library characterization, so this file is provided by the standard cell library vendor.

More details of lib file

Physical libraries: 

The physical library contains the abstract view of the layout for standard cells and macros. LEF file basically contains:

• Size of the cell (Height and width)
• Symmetry of cell
• Pins name, direction, use, shape, layer 
• Pins location

Physical libraries are in Library Exchange Format (.lef) for the Cadence tools or .CELL and .FRAM form for Synopsys tool. This file is provided by the standard cell library vendor.  

More details of LEF file

Technology file: 

The technology library is the most critical input to the physical design tool. The technology library contains detail information about all the metal layers, vias and their design rules. This file is in ASCII format and basically contains the following information:

• Manufacturing grid
• Layers name (poly | contact | metal1 |via2 )
• Types and the direction of the metal
• Pitch
• Width
• Spacing 
• Resistance (per square unit)

The technology file used by the Cadence tool is .techlef format and .tf format by Synopsys tool. 

RC coefficient file: 

TLU file is a short form of "Table Look-Up" is used for RC estimation and extraction or we use QRC file or cap table for the same.

 

MMMC view file: 

Multi-Mode Multi-Corner file is used to generate different analysis views based on different delay corners and constraints modes. Delay corners are defined on library sets and RC corners. There are various library set files based on voltage and temperature values (like ss, ff, typical). 

The above set of files are needed to initiate all the physical design. Some files format is different for the Cadence tool and Synopsys tool. There are some optional files that might be required especially for block-level PnR implementation. These files are as bellow.

Block partition: 

For block-level PnR, we need a defined core area for the block or block partitions which defines the size and shape of the block. Block shape could be a simple rectangular or a complex rectilinear shape.

Pin def: 

For block-level PnR, pin locations have been decided by the Full chip owner and for block-level, we have to use the predecided pin location in order to match the pin locations with other blocks. Generally, it is given in form of a def file. In case of any pin placement issue at the block level, the block owner can inform the person who is placing the pin and if required block owner can also edit the pin placement.

Power plan script: 

For block-level PnR, power plan should be as per the full chip. The power plan has been decided on full chip and in block level, the Power plan should be used as per full chip. Power plan could be given a set of rules or a power plan script (.tcl file).

Power intent (UPF | CPF file): 

Power intent file describes which power rails should be routed to individual block when the block should be powered on or shut down. Unified Power Format (.upf) and Common Power Format (.cpf) are two different formats of power intent files. CPF format is used by the Cadence tool and UPF format by the other tools. We must need this file if the block is having a multi-voltage domain.

Switching activity files (VCD | SAIF): 

SAIF or VCD file is used basically for the dynamic IR analysis in the Physical design. Dynamic IR analysis provides the Dynamic power drop inside the chip based on the switching activities. 

Note:  All the files have described here are very brief, for more details about these files please refer to the "Files in VLSI" section of the blog or our YouTube channel.

Thank you.

Sanity Checks before Floorplan in Physical Design

Sanity checks are an important step for physical design engineers to make sure that the inputs received for physical design are correct and consistent. Any issues in the input files may cause problems in the later stages. So it is important to perform the sanity checks in the initial stage that is when the design is loaded in PnR tool and before the start of the floorplan.

Here is a list of checks which must be performed before the floorplan of design.

Figure-1: Sanity checks before floorplan

Library Check:

In library check, basically, we validate the libraries before starting the physical design by checking the consistency between the physical and logical library.  It also checks the quality of both libraries and reports the error if any. The cells used in the design must be present in the logical as well as in the physical library.

Innovus commands:

checkDesign -physicalLibrary : This command will check the physical library and report that all the cells used in design have their LEF view or not.

checkDesign -timigLibrary : This command will check the timing library and report that all the cells used in design have defined in timing library or not.

checkDesign -all : This command will check the missing or inconsistent library and design data.

ICC command:

check_library : Performs consistency checks between the logical and physical library, across the logical library and within the physical library.

Netlist Check:

Netlist must be checked for consistency. This check analyzes the currently loaded netlist and reports the inconsistency if any. Netlist check mainly checks:

1. Floating input pins and nets
2. No direct connection between VDD and VSS
3. Multidriven nets
4. combinational loops
5. Unloaded outputs
6. Uncontraints pins
7. Mismatch pin count between instance and reference

Innovus command:

checkDesign -netlist

ICC command:

check_design

SDC Check:

SDC file must be checked before start the design. Some of the common issues in SDC file are as follow.

1. Unconstrained path
2. Clock is reaching to all synchronous elements
3. Multiclock driven registers
4. Unconstrained endpoint
5. Input/output delay missing for a port
6. Slew or load constraint missing for a port
7. Missing clock definition

Innovus command:

check_timing

ICC command:

check_timing

Thank you.

Physical Design Flow in details | ASIC Design Flow

 In RTL to GDS flow, Physical Design is an important stage. In physical design, synthesized netlist, design constraints and standard cell library are taken as inputs and converted to a layout (gds file) which should be as per the design rules provided by the foundry.  Further, this layout is sent to the foundry for the fabrication of a chip.

This whole process of converting the gate-level netlist to layout is termed as physical design. In physical design, there are various stages of design, various mandatory checks in each stage and involved various analysis and verifications. In this article, we will see an overall flow of physical design and details of each stage, sanity checks, analysis and verifications will be covered in the coming articles.

Here is a basic physical design flow. There are some minor changes in this flow from company to company.

Figure-1: Basic Physical Design Flow

PrePlacement Stage:

In Physical design, flow start with some set of input files and do the sanity check first once the design is loded into PnR tool. Sanity checks before floor plan are must in order to make sure that netlist, standard cell library and constraint are correct or not. After that floorplan stage starts where the macro placement is done. A good floorplan of design is a critical thing, it decides the overall quality of your design. If floorplan is not well it may lead to several issues in the next stages and it is quite possible that we need to change the floorplan and start again. In general, there are many iterations are required for a physical design engineer to get a quality floorplan. If a block is macro dominant and cell density is high than the floorplan stage is more critical. A good floorplan help to achieve a less congestion and good timing. How to do a good floorplan will be discussed in the other article.

Once the floorplan is done, we need to create the power plan followed by adding antenna diodes, well tap cells, endcap cells, decap cells. What are these cells and why we need will be discussed in the coming article. Generally, this step is called pre-placement stage. Once the preplacement is done we need to again perform a sanity check before the placement stage. 

Placement Stage:

After the preplacement, we do the placement where all the standard cells are placed and legalized. There are various steps placement stage which tool performs, these steps will be discussed on a later article. Once the placement is done we need to perform the optimization for better timing and congestions.

CTS Stage:

Before the Clock Tree Synthesis (CTS) stage the clock is ideal. CTS is a step in which clock is distributed to all the synchronous elements in the design. Before start CTS we need to do sanity checks that the inputs of CTS is proper or not.  In CTS there are basically two steps first build a clock tree and then balance the skew of the clock tree. Quality of CTS is very important in order to meet the timing requirements. A separate article will be done on CTS. After CTS we need to analyze the quality of the clock tree, timing and congestion.

Route Stage:

Route stage comes once the Clock tree is built and routed. In routing, there are basically two stage global routing and detail routing. Power nets and Clock nets are already routed, In this stage, we need to route the data nets. 

Signoff Stage:

Once routing is done we need to insert fillers cells followed by metal fill and then Power signoff, timing signoff, and physical verification. Once all these steps are done in final we stream out the layout in the form of gds or OASIS file which is called tapeout. A detail discussion on each stage will be on coming articles.

* In other files, you may require DEF file, Floorplan file, Power intent (UPF/CPF) file, Technology file, RC coefficient file etc

Thank you.