Input Files Required for PnR and Signoff Stages

In this article, we are going to discuss the input files required in various stages of pnr and signoff. We can categories the set of inputs into two parts, one is mandatory and the other is an optional set of inputs.

A. Place and Route stages:

 

I. Pre Placement Stage

• Gate level netlist 
• Logical Library
• Physical Library
• SDC file

        Optional inputs

• Block partition def
• Pin def
• Power plan script
• Welltap placement rule
• Macro placement guidelines
• MMMC Setup file
• EndCap, Decap cell list
• Spare Cell module definition and rule

Note:  (i) Logical Library, Physical Library and SDC file will be required in each stage.

            (ii) Netlist will get modified in each stage and an updated netlist will be used in the next stage. 

II. Placement

• Preplace database

        Optional Inputs

• Placement blockage script
• Path groups script
• Placement setting script 
• Timing and Congestion Optimization scripts
• Clock tree constraints (In case of Early Clock Flow)

III. CTS

• Placement database
• Clock tree constraints

IV. Route

• CTS database

V. Chip Finish

• Route database
• Filler cell list

B. Metal Fill

• OASIS/GDS of Chip finish stage

C. RC Extraction

• ICT File / Quantus Techfile (qrcTechFile)
• MMMC setup file
• LEF
• DEF
• Merged OASIS/GDS file

D. IR Analysis

Technology/Library Data

• LEF file (.lef)
• LIB file (.lib)
• Technology file (.tech)
• GDS file of standard cells (.gds)
• GDS Layer map file
• Device model file*
• SPICE Netlist of Standard cells* 

Design Data

• DEF file
• Netlist file
• SPEF file
• STA File*  (Timing Window, slew, instance frequency, clock domain info)
• VCD file*
• PLOC file*

* Files required only for dynamic analysis 

Types of Analysis:

I. Static IR Analysis

II. Dynamic IR Analysis

III. EM Analysis

 

E. Static Timing Analysis

• Design Netlist 
• SDC
• LIB
• SPEF
• MMMC view definition file

Optional inputs:

1. Instance-based IR drop file
2. SI library
3. Base/Incr Delay annotation file

F. Physical Verification

I. DRC

• Merged GDS file
• DRC RuleDeck file 

II. Antenna

• Merged GDS file
• Antenna RuleDeck file

III. Layout Vs Schematic Check (LVS)

• PD Netlist
• Merged GDS file 

IV. Logic Equivelence Check (LEC)

• Golden Netlist
• PD Netlist
• LEC Constraints (if any) 

 In case you find anything missing or need a correction, please let me know in the comment section.

Thank You!

Placement Steps in Physical Design

Placement is a very important stage of physical design where all the standard cells get placed inside the core boundary. Overall QoR of the design greatly depends on the fact that how well placement is done. You must have noticed that the placement stage takes quite a large runtime. Actually, the tool performs various steps in a sequence to complete the placement stage. In this article, we will try to understand what are the important steps and the order in which the EDA tools perform to complete the placement stage.

Placement is the process of placing the standard cells inside the core boundary in an optimal location. The tool tries to place the standard cell in such a way that the design should have minimal congestions and the best timing. Every PnR tool provides various commands/switches so that users can optimize the design in a better way in terms of timing, congestion, area, and power as per their requirements. Based on the preferences set by the user, the tool tray to place and optimize it for better QoR. Placement does not place only the standard cells present in the synthesized netlist but also places many physical only cells and adds buffers/inverters as per the requirement to meet the timings, DRV, and foundry requirements. Here are the basic steps which the tool performs during the placement and optimization stage.

placement steps:

1. Pre Placement
2. Initial Placement / Course Placement / Global Placement
3. Legalization
4. HFNS (Hign Fanout Net Synthesis)
5. Iteration for Congestion, Timing, DRV, and Power Optimization
6. Multibit flop conversion
7. Timing optimization iterations
8. Scan-Chain Reorder
9. Tie Cell insertion
10. Save Design

1. Pre Placement:

Figure-1: Pre-placement step

Before starting the actual placement of the standard cells present in the synthesized netlist, we need to place various physical only cells like end-cap cells, well-tap cells, IO buffers, antenna diodes, and spare cells. A typical view after preplacement has shown in figure-1. Why these cells are required to place and how do we place them has been discussed separately in this article. Here we will focus mainly on the placement steps of standard cells present in the synthesized netlist.

2. Initial Placement / Global Placement / Course Placement 

Figure-2: Global placement before legalization

Once the pre Placement stage has been completed, We can start the placement of standard cells but before that, we have to provide all the correct placement and optimization settings that we want to be applied while the tool does the placement and optimization. These settings could be like partial placement blockage or density screen setting, bound or region creation, cell/instance padding, path_groups and effort, enabling the early clock flow (ECF) in case of innovus, enabling the extreme flow, enabling the useful skew, global congestion effort, global timing effort, power effort, Multibit flop conversion and many more.

After providing all these placement settings we can call the placement command (place_opt_design in case of innovus). The tool first does the global placement in which the tool determines the approximate location of each cell according to the timing, congestion, and multi-voltage constraints (in the case of innovus Gigaplace engine is called in this step). Any pre-placed macros will work as a placement blockage. In this stage, the tool will not check any overlap of instances. A typical figure of global placement has shown in figure-2 where you can see that the standard cells are placed in an approximate location but without legalization. 

3. Legalization

In the global placement stage, the instances are left with overlap. In this step, the tool will move the instances in nearby places to overcome the overlap. To match the proper power pins like the vdd pin of a standard cell should be on the vdd rail and vss on vss rail and for that if the fliping of instance is required tool also do the flipping. This process is called legalization. After this step, every instance should be placed in a legal location and there should be no overlaps. This step is also called refine placement.

4. HFNS (Hign Fanout Net Synthesis)

Initially, there are some nets which have very high numbers of fanout. We have a constraint of maximum fanout, so we need to distribute the sinks on nets to different drivers. The process of adding buffers and splitting the fanout is called high fanout net synthesis (HFNS). So In this step, all high fanout nets get synthesized.

5. Iteration for Congestion, Timing, DRV, and Power Optimization

In this step tool first, do an early global route and estimate the routing overflow/congestions in the design. The tool tries to initially minimize the congestion in this stage. Next, the tool starts the RC extraction to calculate the delay for setup analysis. The tool tries to minimize the setup WNS and TNS in this step. Similarly, the tool also tries to minimize the DRV and Power in this stage.

6. Multibit flop conversion

If the user enables the multi-bit flip flop conversion in the flow then the tool will first check the available multibit flops in the library. (You can read more about multi-bit cell here) The tool considers the criticality of timing associated with a single bit of flop and the user constraint set for multi-bit conversion and based on the constraints the tool converts the single-bit flop into multibit flops.

7. Timing optimization iterations

This is a long step in which the tool tries to minimize the WNS and TNS of each path group in various iterations. There are several iterations required to get a minimum WNS and TNS depending upon the effort set and initial WNS number. In case the result is not good after this stage, we can further run incremental optimization for timing. Similarly, for congetion, we can run congestion repair followed by incremental optimization to get a better result. But these additional steps will increse the run time.

8. Scan-Chain Reorder

Figure-3: Scan Chain before placement

Scan chain stitching has been done arbitrarily in synthesis. After placement and optimization, we have a location for each scan flops so it needs to be reordered for better routability. The tool performs a reordering of the scan chain in this step which is good for both timing and congestions. 

Figure-4: Scan chain after placement

Figure-5: Scan Chain after Scan chain reodrder

 

9. Tie Cell insertion

There are some unused inputs of logic gates in the netlist which is tied to either vdd or vss. We can not leave any inputs of the standard cell as floating, it must be tied either vdd or vss. Connecting an input of logic cell that is the gate of a transistor directly to vdd or vss is not recommended and for that, we have tie high and tie low cells in the library. (You may watch this video on tie cells for more details). So In this step tool places tie high and tie low cells which is basically a single output logic cell, and it connects the input of the logic gate which needs to connect vdd or vss respectively. 

10. Save Design

Finally, we save the database and we will use this database in the next stage, that is in the clock tree synthesis.

Inputs for Physical Design | Physical Design input files

In this article, we will discuss what are the inputs required to begin the physical design. In the previous article, we have discussed the physical design flow and sanity checks before the floorplan. Inputs required for physical design can be categories broadly into two types. Some inputs are mandatory in all the cases but some are required for a specific purpose. Figure-1 shows the list of inputs required for physical design and categories the mandatory and optional inputs.

Figure-1: Inputs for Physical Design

In the set input files, the first set is design-related files which contain Gate level netlist file and design constraint files. These files come from the synthesis team. Let's briefly see the content of these files.

Gate level netlist: 

This is the synthesized netlist. The synthesis team performs synthesis on RTL code with the standard cell libraries and constraints and converts the RTL code into the gate-level netlist based on available standard cells. This file contains all the instances of design and their connection. 

 

Constraint file: 

Constraint file is popularly known as SDC file by its extension of the file. It contains basically,

• Units (Time, Capacitance, Resistance, Voltage, Current, Power)
• System interface (Driving cell, load)
• Design rule constraints (max fanout, max transition)
• Timing constraints (Clock definitions, clock latency, clock uncertainty, input/output delay)
• Timing exceptions (Multi-cycle and false paths)

A detail description of SDC file is explained here

Now some inputs are required which are related to standard cell libraries. These files are provided by the standard cell library vendor and these files are as follow. 

Logical libraries: 

The logical library is also called a timing library or functional library or power library as it contains the functionality, time and power information of cells. This file contains basically the following information of the standard cells or macros. 

• Timing details of the standard cells / macros ( delay, transitions)
• Setup and hold time of  standard cells / macros
• Functionality details of  standard cells /macros
• Area of standard cells / macros
• Pin directions and capacitance
• Leakage power of standard cells / macros 

The logical libraries could be either in liberty format .lib file for Cadence tool or in the form of .db file for Synopsys tool. There are different logical files for different PVT corners. Liberty file is created by doing the standard cell library characterization, so this file is provided by the standard cell library vendor.

More details of lib file

Physical libraries: 

The physical library contains the abstract view of the layout for standard cells and macros. LEF file basically contains:

• Size of the cell (Height and width)
• Symmetry of cell
• Pins name, direction, use, shape, layer 
• Pins location

Physical libraries are in Library Exchange Format (.lef) for the Cadence tools or .CELL and .FRAM form for Synopsys tool. This file is provided by the standard cell library vendor.  

More details of LEF file

Technology file: 

The technology library is the most critical input to the physical design tool. The technology library contains detail information about all the metal layers, vias and their design rules. This file is in ASCII format and basically contains the following information:

• Manufacturing grid
• Layers name (poly | contact | metal1 |via2 )
• Types and the direction of the metal
• Pitch
• Width
• Spacing 
• Resistance (per square unit)

The technology file used by the Cadence tool is .techlef format and .tf format by Synopsys tool. 

RC coefficient file: 

TLU file is a short form of "Table Look-Up" is used for RC estimation and extraction or we use QRC file or cap table for the same.

 

MMMC view file: 

Multi-Mode Multi-Corner file is used to generate different analysis views based on different delay corners and constraints modes. Delay corners are defined on library sets and RC corners. There are various library set files based on voltage and temperature values (like ss, ff, typical). 

The above set of files are needed to initiate all the physical design. Some files format is different for the Cadence tool and Synopsys tool. There are some optional files that might be required especially for block-level PnR implementation. These files are as bellow.

Block partition: 

For block-level PnR, we need a defined core area for the block or block partitions which defines the size and shape of the block. Block shape could be a simple rectangular or a complex rectilinear shape.

Pin def: 

For block-level PnR, pin locations have been decided by the Full chip owner and for block-level, we have to use the predecided pin location in order to match the pin locations with other blocks. Generally, it is given in form of a def file. In case of any pin placement issue at the block level, the block owner can inform the person who is placing the pin and if required block owner can also edit the pin placement.

Power plan script: 

For block-level PnR, power plan should be as per the full chip. The power plan has been decided on full chip and in block level, the Power plan should be used as per full chip. Power plan could be given a set of rules or a power plan script (.tcl file).

Power intent (UPF | CPF file): 

Power intent file describes which power rails should be routed to individual block when the block should be powered on or shut down. Unified Power Format (.upf) and Common Power Format (.cpf) are two different formats of power intent files. CPF format is used by the Cadence tool and UPF format by the other tools. We must need this file if the block is having a multi-voltage domain.

Switching activity files (VCD | SAIF): 

SAIF or VCD file is used basically for the dynamic IR analysis in the Physical design. Dynamic IR analysis provides the Dynamic power drop inside the chip based on the switching activities. 

Note:  All the files have described here are very brief, for more details about these files please refer to the "Files in VLSI" section of the blog or our YouTube channel.

Thank you.

Sanity Checks before Floorplan in Physical Design

Sanity checks are an important step for physical design engineers to make sure that the inputs received for physical design are correct and consistent. Any issues in the input files may cause problems in the later stages. So it is important to perform the sanity checks in the initial stage that is when the design is loaded in PnR tool and before the start of the floorplan.

Here is a list of checks which must be performed before the floorplan of design.

Figure-1: Sanity checks before floorplan

Library Check:

In library check, basically, we validate the libraries before starting the physical design by checking the consistency between the physical and logical library.  It also checks the quality of both libraries and reports the error if any. The cells used in the design must be present in the logical as well as in the physical library.

Innovus commands:

checkDesign -physicalLibrary : This command will check the physical library and report that all the cells used in design have their LEF view or not.

checkDesign -timigLibrary : This command will check the timing library and report that all the cells used in design have defined in timing library or not.

checkDesign -all : This command will check the missing or inconsistent library and design data.

ICC command:

check_library : Performs consistency checks between the logical and physical library, across the logical library and within the physical library.

Netlist Check:

Netlist must be checked for consistency. This check analyzes the currently loaded netlist and reports the inconsistency if any. Netlist check mainly checks:

1. Floating input pins and nets
2. No direct connection between VDD and VSS
3. Multidriven nets
4. combinational loops
5. Unloaded outputs
6. Uncontraints pins
7. Mismatch pin count between instance and reference

Innovus command:

checkDesign -netlist

ICC command:

check_design

SDC Check:

SDC file must be checked before start the design. Some of the common issues in SDC file are as follow.

1. Unconstrained path
2. Clock is reaching to all synchronous elements
3. Multiclock driven registers
4. Unconstrained endpoint
5. Input/output delay missing for a port
6. Slew or load constraint missing for a port
7. Missing clock definition

Innovus command:

check_timing

ICC command:

check_timing

Thank you.

Physical Design Flow in details | ASIC Design Flow

 In RTL to GDS flow, Physical Design is an important stage. In physical design, synthesized netlist, design constraints and standard cell library are taken as inputs and converted to a layout (gds file) which should be as per the design rules provided by the foundry.  Further, this layout is sent to the foundry for the fabrication of a chip.

This whole process of converting the gate-level netlist to layout is termed as physical design. In physical design, there are various stages of design, various mandatory checks in each stage and involved various analysis and verifications. In this article, we will see an overall flow of physical design and details of each stage, sanity checks, analysis and verifications will be covered in the coming articles.

Here is a basic physical design flow. There are some minor changes in this flow from company to company.

Figure-1: Basic Physical Design Flow

PrePlacement Stage:

In Physical design, flow start with some set of input files and do the sanity check first once the design is loded into PnR tool. Sanity checks before floor plan are must in order to make sure that netlist, standard cell library and constraint are correct or not. After that floorplan stage starts where the macro placement is done. A good floorplan of design is a critical thing, it decides the overall quality of your design. If floorplan is not well it may lead to several issues in the next stages and it is quite possible that we need to change the floorplan and start again. In general, there are many iterations are required for a physical design engineer to get a quality floorplan. If a block is macro dominant and cell density is high than the floorplan stage is more critical. A good floorplan help to achieve a less congestion and good timing. How to do a good floorplan will be discussed in the other article.

Once the floorplan is done, we need to create the power plan followed by adding antenna diodes, well tap cells, endcap cells, decap cells. What are these cells and why we need will be discussed in the coming article. Generally, this step is called pre-placement stage. Once the preplacement is done we need to again perform a sanity check before the placement stage. 

Placement Stage:

After the preplacement, we do the placement where all the standard cells are placed and legalized. There are various steps placement stage which tool performs, these steps will be discussed on a later article. Once the placement is done we need to perform the optimization for better timing and congestions.

CTS Stage:

Before the Clock Tree Synthesis (CTS) stage the clock is ideal. CTS is a step in which clock is distributed to all the synchronous elements in the design. Before start CTS we need to do sanity checks that the inputs of CTS is proper or not.  In CTS there are basically two steps first build a clock tree and then balance the skew of the clock tree. Quality of CTS is very important in order to meet the timing requirements. A separate article will be done on CTS. After CTS we need to analyze the quality of the clock tree, timing and congestion.

Route Stage:

Route stage comes once the Clock tree is built and routed. In routing, there are basically two stage global routing and detail routing. Power nets and Clock nets are already routed, In this stage, we need to route the data nets. 

Signoff Stage:

Once routing is done we need to insert fillers cells followed by metal fill and then Power signoff, timing signoff, and physical verification. Once all these steps are done in final we stream out the layout in the form of gds or OASIS file which is called tapeout. A detail discussion on each stage will be on coming articles.

* In other files, you may require DEF file, Floorplan file, Power intent (UPF/CPF) file, Technology file, RC coefficient file etc

Thank you.

ASIC Design Flow - An Overview

In this post, ASIC (Application Specific Integrated Circuit) Design flow has been explained. The very first step of ASIC flow is design specification, which comes from the customer end. Where customer writes down the specification of the chip basically the functionality which he wants to develop in a chip.  The whole design process is going through various design cycles and it generally takes 6 to 24 months to complete the design depending on the complexity inside the chip.
The complete ASIC design process can be divided into two parts.

1. Front End Design
2. Back End Design

Front End Design:

Front end design process starts with the specification received from the customer end. RTL (Register Transfer Level) design engineer converts the specification into an RTL code using the HDL (Hardware Description Language) generally either in Verilog or VHDL. Once the RTL code is written, RTL designer simulates the code in RTL Simulator and check the functionality of the design. Once the functionality of code is correct and verified by the verification engineers and if there is no bug found, This RTL code is taking to the next stage which is logic synthesis. This flow starts with RTL coding and ends with GDS (Graphic Data Stream)  file which is the final output of back end design, so this complete flow is also known as RTL to GDS (RTL2GDS) flow. A Simple flow diagram has been described here. 

Back End Design:

RTL code received from the front end engineer is technology independent, now the next step is Logic synthesis. 

Logic Synthesis:  In logic synthesis, a high-level description of the design (RTL Code) is converted into an optimized gate-level representation of a given standard cell library and certain design constraints. Now the code is in the form of a gate-level netlist of a particular standard cell library. LEC (Logic Equivalence Check is must in this stage to make sure that there are not logical changes occurred during the synthesis. During logical Synthesis, we also get various reports on timing power and area of design. We also get an SDC (Synopsys Design Constraint) file in this stage which is used in the next stage. DFT (Design For Testability) Insertion is also done in this stage to verify the chip after fabrication is done. 

Place and Route (PnR): Gate level netlist after DFT Insertion and SDC file is taken as input for the PnR and based on standard cells library, PnR starts. The goal of PnR stage is to place all the standard cells, Macros and I/O pads with minimal area, with minimal delay and Route them together in such a way that there is no DRC (Design Rule Check) error. The final output of this stage is the layout of design in the form of GDSII file which is defacto standard of layout file in the industry. 

PnR stage is a very challenging stage with large design cycle time depending on the complexity of a chip. This stage is further divided into various sub-stages. The main stages are starting from Design Import, followed by FloorPlan, Power Plan, Placement, CTS (Clock Tree Synthesis), and Routing. 

After routing we expect the design has met the timing and all DRC, But in the modern chip, it's not easy to close the design in this stage. So Further we go to Signoff stage.

Signoff: If there are some timing violations in post route design, we have a further stage called ECO (Engineering Change Order) where we can fix the timing violations. Apart from timing violation, there may be issues like IR Drop, DRC Violations all these are fixed in this stage and a final layout file free from all the violation is streamed out in GDSII format. This process is known as tapeout in ASIC flow. This is the final design stage and gdsII file is sent to fabrication lab for the fabrication of chip.

Thank you.