IO Interface Analysis: Constraints for IO pins on block level

We all know that all the input and output pins of a block must be constrained in order to enable the PnR tool to optimize those interface paths. How to constrain an input or output pin will be discussed in this article. We will also discuss what are the actual meanings of these constraints and how these constraints affect the timing analysis.

In the above figure, there are two timing paths shown, one is from CIN to FF1 and other is from FF2 to COUT. The path from CIN to FF1 is called input to register (In2Reg) path whereas the path from FF2 to COUT is called register to output (Reg2Out) path. Any timing paths which are related to an input and output pins is called Interface timing path.

Input Interface:

If we consider a block-level PnR implementation, the input to register path might be a part of the register to register path as shown in the above figure. Register FF11 is outside of the block but a part of the path from CIN to FF1 is inside the block. So in order to meet the timing of register to register path FF11 to FF1, we can divide this path into two parts. 

First part is the delay between the clock pin of FF11 to the input pin of block CIN and the second part is the delay from CIN pin to the D pin of FF1 as shown in the above figure. the first part is called input delay of the CIN pin. Since this path is out of the block so there is no timing information if this path can not be calculated by the tool. So we need to provide the delay of this part of the path as an input delay of pin CIN in SDC file. based on this input delay value PnR tool will estimate the timing margin from CIN to D pin of FF1 and optimize the path. On the block level, we need to close the timing from CIN to FF1 only that is Input to register path. 

For Example, 

    let's say the clock period is 1ns.

    And for setup analysis, the data required time for the path FF11 to FF1 is 850ps. 

    Suppose the maximum delay of the path from the clock pin of FF11 to CIN  is 550ps.

     Then on block-level, for setup analysis, we have to close the remaining path that is from CIN to FF1 at 850 - 550 = 300ps.

Input delay path has also two parts, one is clock to q dealy of FF11 and other is a combinational delay from q to CIN. This path will have max and min delay, which will be used separately in the setup and hold analysis. So when we apply input delay we apply two delays, max input delay and min input delay. The command for applying this delay in the SDC file is as follow.

Setting Input Delay:

create_clock -name RLCK -period 1 [get_ports RCLK]

set_input_delay -max 0.55 -clock RCLK [get_ports CIN]

set_input_delay -min 0.45 -clock RCLK [get_ports CIN]

The above set of SDC commands will set the maximum input delay of 550 ps and minimum input delay 450 ps to CIN input pin. We can understand this in a more simple way that data will be launched from the CIN pin after the input delay. So more input delay means lesser time available to reach the data to capture flop FF1. A similar logic is applicable for hold analysis too. 

Output Interface:

In block level, the register to output path from FF2 to COUT is a part of the complete path from FF2 to FF22 as shown in the above figure. Flip flop FF22 and the path from COUT to the FF22 is outside the block and this path can be supposed here a virtual path.

The path from FF2 to FF22 might be thought as two parts as shown in the above figure. part-1 is from FF2 to COUT which is inside the block and part-2 from COUT to FF22 which is outside the block and virtual here. Delay of part-2 path is called the output delay of the COUT pin. This delay is the combinational delay before the register FF22 and outside the block. This part will have a maximum and minimum delay which we need to specify while specifying the output delay for pin COUT.

For Example, 

    let's say the clock period is 1ns.

    And for setup analysis, the data required time for the path FF2 to FF22 is 800ps. 

    Suppose the max delay of the path-2  from COUT  to FF222 is 250ps.

     Then on block-level, for setup analysis, we have to close the remaining path from FF2 to COUT at 800 - 250 = 550ps.

In SDC file we specify maximum and minimum output delay, which is used separately for setup and hold analysis. The output delay is the delay from the output pin to the next register.  

Setting Output Delay:

create_clock -name RLCK -period 1 [get_ports RCLK]

set_output_delay -max 0.25 -clock RCLK [get_ports COUT]

set_output_delay -min 0.20 -clock RCLK [get_ports COUT]

The above set of SDC commands will set the maximum output delay of 250 ps and minimum input delay 200 ps to COUT output pin. We can imagine this like there is a virtual flop outside the block and the delay from COUT pin to that virtual flop is output delay of COUT pin. Here output delay has explained with reference to setup analysis but a similar concept is applicable for the hold analysis too. 

Thanks!

Inputs for Physical Design | Physical Design input files

In this article, we will discuss what are the inputs required to begin the physical design. In the previous article, we have discussed the physical design flow and sanity checks before the floorplan. Inputs required for physical design can be categories broadly into two types. Some inputs are mandatory in all the cases but some are required for a specific purpose. Figure-1 shows the list of inputs required for physical design and categories the mandatory and optional inputs.

Figure-1: Inputs for Physical Design

In the set input files, the first set is design-related files which contain Gate level netlist file and design constraint files. These files come from the synthesis team. Let's briefly see the content of these files.

Gate level netlist: 

This is the synthesized netlist. The synthesis team performs synthesis on RTL code with the standard cell libraries and constraints and converts the RTL code into the gate-level netlist based on available standard cells. This file contains all the instances of design and their connection. 

 

Constraint file: 

Constraint file is popularly known as SDC file by its extension of the file. It contains basically,

• Units (Time, Capacitance, Resistance, Voltage, Current, Power)
• System interface (Driving cell, load)
• Design rule constraints (max fanout, max transition)
• Timing constraints (Clock definitions, clock latency, clock uncertainty, input/output delay)
• Timing exceptions (Multi-cycle and false paths)

A detail description of SDC file is explained here

Now some inputs are required which are related to standard cell libraries. These files are provided by the standard cell library vendor and these files are as follow. 

Logical libraries: 

The logical library is also called a timing library or functional library or power library as it contains the functionality, time and power information of cells. This file contains basically the following information of the standard cells or macros. 

• Timing details of the standard cells / macros ( delay, transitions)
• Setup and hold time of  standard cells / macros
• Functionality details of  standard cells /macros
• Area of standard cells / macros
• Pin directions and capacitance
• Leakage power of standard cells / macros 

The logical libraries could be either in liberty format .lib file for Cadence tool or in the form of .db file for Synopsys tool. There are different logical files for different PVT corners. Liberty file is created by doing the standard cell library characterization, so this file is provided by the standard cell library vendor.

More details of lib file

Physical libraries: 

The physical library contains the abstract view of the layout for standard cells and macros. LEF file basically contains:

• Size of the cell (Height and width)
• Symmetry of cell
• Pins name, direction, use, shape, layer 
• Pins location

Physical libraries are in Library Exchange Format (.lef) for the Cadence tools or .CELL and .FRAM form for Synopsys tool. This file is provided by the standard cell library vendor.  

More details of LEF file

Technology file: 

The technology library is the most critical input to the physical design tool. The technology library contains detail information about all the metal layers, vias and their design rules. This file is in ASCII format and basically contains the following information:

• Manufacturing grid
• Layers name (poly | contact | metal1 |via2 )
• Types and the direction of the metal
• Pitch
• Width
• Spacing 
• Resistance (per square unit)

The technology file used by the Cadence tool is .techlef format and .tf format by Synopsys tool. 

RC coefficient file: 

TLU file is a short form of "Table Look-Up" is used for RC estimation and extraction or we use QRC file or cap table for the same.

 

MMMC view file: 

Multi-Mode Multi-Corner file is used to generate different analysis views based on different delay corners and constraints modes. Delay corners are defined on library sets and RC corners. There are various library set files based on voltage and temperature values (like ss, ff, typical). 

The above set of files are needed to initiate all the physical design. Some files format is different for the Cadence tool and Synopsys tool. There are some optional files that might be required especially for block-level PnR implementation. These files are as bellow.

Block partition: 

For block-level PnR, we need a defined core area for the block or block partitions which defines the size and shape of the block. Block shape could be a simple rectangular or a complex rectilinear shape.

Pin def: 

For block-level PnR, pin locations have been decided by the Full chip owner and for block-level, we have to use the predecided pin location in order to match the pin locations with other blocks. Generally, it is given in form of a def file. In case of any pin placement issue at the block level, the block owner can inform the person who is placing the pin and if required block owner can also edit the pin placement.

Power plan script: 

For block-level PnR, power plan should be as per the full chip. The power plan has been decided on full chip and in block level, the Power plan should be used as per full chip. Power plan could be given a set of rules or a power plan script (.tcl file).

Power intent (UPF | CPF file): 

Power intent file describes which power rails should be routed to individual block when the block should be powered on or shut down. Unified Power Format (.upf) and Common Power Format (.cpf) are two different formats of power intent files. CPF format is used by the Cadence tool and UPF format by the other tools. We must need this file if the block is having a multi-voltage domain.

Switching activity files (VCD | SAIF): 

SAIF or VCD file is used basically for the dynamic IR analysis in the Physical design. Dynamic IR analysis provides the Dynamic power drop inside the chip based on the switching activities. 

Note:  All the files have described here are very brief, for more details about these files please refer to the "Files in VLSI" section of the blog or our YouTube channel.

Thank you.

Synopsys Design Constraints | SDC File in VLSI

SDC is a short form of "Synopsys Design Constraint". SDC is a common format for constraining the design which is supported by almost all Synthesis, PnR and other tools. Generally, timing, power and area constraints of design are provided through the SDC file and this file has extension .sdc. 

SDC file syntax is based on TCL format and all commands of sdc file follow the TCL syntax. In sdc file '#' is used to comment a line and '\' is used to break the line. SDC file can be generated by the synthesis tool and the same can be used in for PnR.

Constraints in SDC file

Inside the sdc file, some important constraints are as follow.

1. SDC Version: 

This statement specifies the version of the SDC file. it could be 2.1, 2.0, 1.9 or more older.

Version 2.1 has introduced in December 2017.

Example: 

set sdc_version 2.1

2. Units: 

Units of various quantities like time, resistance, capacitance, voltage, current, and power can be specified using set_unit command.

Multiples units can be set using a single set_unit command.

Example: 

set_units -time ns -resistance Kohm -capacitance pF -voltage V -current mA

SDC commands could be further categories as follow. Some important commands will be discussed in the later section.

A.  Operating Conditions

B.  Wire Load Models

C.  System Interface

Let's discuss some important System Interface constraints in this section.

3. Set driving cells: 

specifies the drive characteristics of input or inout ports that are driven by the cells in the technology library. These commands associate a library pin with input ports so that delay calculation can be accurately modelled.

Syntax:

set_driving_load [-lib_cell lib_cell_name] [-library lib_name] [-rise] [-fall] [-min] [-max] [-pin pin_name] [-from_pin from_pin_name] [-dont_scale] [-no_design_rule] [-input_transition_rise rtrans] [-input_transition_fall ftrans] [-multiply_by_facrtor] [-clock clock_name] [-clock_fall] port_list 

Example: 

set_driving_cell -lib_cell IV {I1}

set_driving_cell -lib_cell AND2 -pin Z -from_pin B {I2} 

4. Set load: 

This command sets the load attributes on the specified ports and the nets in the current design. Unit of load value will be the unit of capacitance specified in the unit defined in this file.

Syntax:

set_load value objects [-subtract_pin_load] [-min] [-max] [[-pin_load] [-wire_load]]

Example:

set_load -pin_load 0.001 [get_ports {port[10]}]

D.  Design Rule Constraints

In this part basically maximum fanout, maximum and minimum capacitance,  and  maximum transition time are set

5. Set maximum fanout: 

Maximum fanout load is set to a specific input port and/or design

Syntax:

set_max_fanout fanout_value object_list 

Example:

set_max_fanout 5 [get_ports {port[10]}]

6. Set maximum transition: 

Maximum transition time is set by this command which is a design rule and set to clock port or design is set to a specific input port and/or design.

Syntax:

set_max_transition transition_value [-data_path] [-clock_path] object_list 

Example:

set_max_transition 2.5 [get_ports IN]

E.  Timing Constraints

In this part basically, we set clocks definition, clock group, clock latency, clock uncertainty, clock transition, input delay, output delay, timing derates etc.

7. Create clock: 

Syntax:

create_clock [-name clock_name] [clock_sources] [-period value] [-waveform edge_list] [-add] [-comment] 

The create_clock command creates a clock object in the current design. This command defines the specified source_objects as a clock source.

Example:

create_clock "u13/z" -name "CLK" -period 30 -waveform {12.0 27.0}

create_clock -name "PH12" -period 10 -waveform {0.0 5.0}

8. Create generated clock: 

Syntax:

create_generated_clock [-name clock_name] [-add] source_objects -source master_pin [-master_clock clock] [-divide_by divide_factor | -multiply_by multiply_factor ] [-duty_cycle percent] [-invert] [-preinvert] [-edges edge_list] [-edge_shift edge_shift_list] [-combinational]

The create_generated_clock command creates a generated clock object. A pin or port could be specified for the generated clock object. Generated clock follow the master clock, so whenever the master clock changes generated clock will change automatically. A generated clock can be created as a frequency-divided clock,  a frequency multiplied clock, an edge divided clock or an inverted clock.

Example:

create_generated_clock -multiplied_by 3 -source CLK [get_pins div3/Q]

The above example will generate a clock which is derived from the original clock named CLK. The generated clock will have a frequency 3 times of the original clock and time period will be one-third of the original (15ns --> 5ns).

9. Group path:

Syntax:

group_path [-weight weight_value] [-critical_range range_value] -default | -name group_name [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through trough_list | -rise_through rise_through_list -fall_through fall_through_list] [-to to_list | -rise_to rise_to_list | -fall_to fall_to_list] [-comment comment_string] [-priority priority_level]

Groups are a set of paths or endpoints for the cost function calculations. The group enables us to specify a set of paths to optimize even though there may be a larger violation in other groups. When endpoints have specified all paths leading to those end paths are grouped. 

The create_clock command automatically creates a group for the new clock with a weight of 1.0 and named the same as the clock name. 

Example:

group_path -name "group1" -weight 2.0 -to {CLK1A CLK1B}

group_path -name GROUP1 -from [get_ports ABC/in3] -to [get-ports FF1/D]

 10. Clock uncertainty:

Syntax:

set_clock_uncertainity [object_list | -from from_clock | -rise_from rise_from_clock | -fall_from fall_from_clock -to to_clock | -rise_to rise_to_clock | -fall_to fall_to_clock] [rise] [-fall] [-setup] [-hold] uncertainty 

After defining the clock, to take care of variance in the clock network clock uncertainty added. Clock uncertainty adds some margin of error into the system to account for variance in the clock network caused by non-ideality of clock network and clock source itself.

Above specified command can specify either inter-clock uncertainty or simple uncertainty. It sets uncertainty to the worst skew expected to the endpoints or between the clock domains. 

Example:

set_clock_uncertainty -setup 0.5 [get_clocks clk1]

set_clock_uncertainty -hold 0.2 [get_clocks clk1]

Clock uncertainty can also be added for rise and fall time of clock as bellow.

set_clock_uncertainty -max_rise 0.12 [get_clocks clk1]

set_clock_uncertainty -max_fall 0.12 [get_clocks clk1]

set_clock_uncertainty -min_rise 0.12 [get_clocks clk1]

set_clock_uncertainty -min_fall 0.12 [get_clocks clk1]

11. Clock latency:

Syntax:

set_clock_latency [-rise] [-fall] [-min] [-max] [-source] [-early] [-late] [-dynamic jitter] [-clock clock_list] delay object_list

Clock latency specifies the amount of delay for a clock signal reaching to the clock pin of a sequential element from the clock source pin. There are two types of clock latency one is network latency (default) and other is source latency (by using the -source option)

Clock network latency is the time taken by the clock signal to propagate from the clock definition point to the clock pin of a register. Whereas source latency is the time taken by a clock signal to propagate from actual-ideal waveform origin point to the clock definition point in the design. Source delay is also called an insertion delay.  

Example:

set_clock_latency 2.35 [get_pins ABC/XYZ/CP] 

12. Input delay:

Syntax:

set_input_delay delay_value [-reference_pin pin_port_name] [-clock clock_name] [-level_sensitive] [-network_latency_included] [-source-latency_included] [-rise] [-fall] [-min] [-max] [-add_delay] port_pin_list

Input delay defines the time requirements of an input port with respect to clock edge. Input ports are assumed to have zero input delay if it is not specified. The delay value to be specified is the delay between the start point and the object on which set_input_delay is being set relative to the clock edge.

Example:

set_input_delay -max 1.35 -clock clk1 {ain bin} 

13. Output delay:

Syntax:

set_output_delay delay_value [-reference_pin pin_port_name] [-clock clock_name] [-clock_fall] [-level_sensitive] [-network_latency_included] [-source-latency_included] [-rise] [-fall] [-min] [-max] [-add_delay] [-group_path group_name] port_pin_list

set_output_delay command sets output delay requirements on an output port with respect to the clock edge. Output ports are assumed to have zero output delay if it is not specified. 

Example:

set_output_delay 1.7 -clock [get_clocks CLK1] [all_outputs]

Above command will set output delay 1.7 unit to all output ports with respect to the positive edge (default edge) of the CLK1.

set_output_delay -max 1.4 -clock {CLK} [get_ports {Y}]

set_output_delay -min 1.0 -clock {CLK} [get_ports {Y}]

In above command -max value refers to the longest path and -min value refers to the shortest path. If no -max or -min value is specified, maximum and mimum output delays are assumed to be equal.

E.  Timing Exceptions

In this part, some of the important constraints like false paths, multicycle paths, maximum delay and minimum delay are defined. 

14. Multicycle paths: 

Syntax:

set_multicycle_path path_multiplier [-rise | -fall] [-setup | -hold] [-start | -end] [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through through_list] [-rise_through rise_through_list] [-fall_through fall-through_list] [-to to_list | -rise_to rise_to_list | -fall_to fall_to_list] [-reset_path] 

A multicycle path is an exception of the default single-cycle timing requirement path. In a multicycle path, signal requires more than one single clock cycle to propagate from the start point to the endpoint of the path. This command specifies the number of cycles the data path must have for setup or hold check. The following command will set a constraint of two cycles path from source point A to endpoint B. 

Example:

set_multicycle_path 2 -from A -to B 

set_multicycle_path 3 -from C 

We can add a -through point between source and endpoint and also we can set multicycle path to all paths my mentioning only source or only endpoint. 

15. False paths: 

Syntax:

set_false_path [-rise] [-fall] [-setup] [-hold] [-from from_list | -rise_from rise_from_list | -fall_from fall_from_list] [-through through_list] [-rise_through rise_through_list] [-fall_through fall-through_list] [-to to_list | -rise_to rise_to_list | -fall_to fall_to_list] [-reset_path] 

A false path is a path that can not propagate a signal. For example, a path that never activates by any combination of inputs is a false path. False paths should be disabled for timing analysis. The SDC command set_false_path is used to define the false paths. False paths will be excluded for timing analysis. 

Example:

set_false_path -from U1/G -to U1/D 

set_false_path -from {ff12} -to {ff34}

Summary: 

This article has described 15 most important constraints in SDC file. There are many more constraints for a complex design. Here is the summary of all discussed constraints. 

1. SDC Version
2. Units
System Interface
3. Set driving cells
4. Set load
Design rule constraints
5. Set maximum fanout
6. Set maximum Transition
Timing constraints
7. Create Clock
8. Create Generated Clock

9. Group Path
10. Clock Uncertainty
11. Clock Latency
12. Input Delay
13. Output Delay
Timing Exception
14. Multicycle Path
15. False Path 

Thank you.