Contents

All Content of teamVLSI blog (clickable)

For the better experience of readers of teamVLSI blog, Here a topic-wise contest list provided which will help to explore the blog in a better way. One can read any topics from this list by just clicking the name of topics.

	S.No	Topics	A. No.	Articles
	1	ASIC Flow	1	ASIC Design flow
			2	Physical Design flow in Details
			3	Inputs for Physical Design
			4	Sanity checks before floorplan in Physical Design
	2	Files in VLSI	3*	Inputs for Physical Design
			5	LIB file in VLSI
			6	LEF file in VLSI
			7	DEF file in VLSI
			8	SDC file in VLSI
			31*	Clock Tree Constraints File
	3	Issues in VLSI	9	Latchup issue in VLSI
			10	Latchup prevention techniques in VLSI
			##	Well tap cells and latchup prevention mechanism
			11	Antenna effect in VLSI
			12	Antenna prevention techniques in VLSI
			13	Electromigration effect in VLSI
			14	Signal Intigrity and crosstalk effect in VLSI
			15	Crosstalk Noise and crosstalk delay effect
			16	Crosstalk timign window analysis and prevention techniques
			17	IR drop analysis in VLSI
			18	OCV in Physical Design
			19	OCV, AOCV and POCV in VLSI
	4	Standard Cell	20	Standard cells library for ASIC Design
			21	Standard cells in ASIC Design
			22	Well Tap cells in Physica Design
			23	EndCap/Boundry cells in Physica Design
			24	Decap cells in Physical Design
			25	Spare Cells in Physical Design
			26	Integrated Clock Gating (ICG) Cell in VLSI
			27	Tie Cells in Physical Design
			30*	Multi-bit flip flops Vs Single-bit flip flops
			28	Flip-flop and Latch : Internal structures and Functions
	5	Short Topics	29	Temperature Inversion in VLSI
			30	Multi-bit flip flops Vs Single bit flip flops
	6	Pre Placement	31	Floorplan Strategy for macro dominating blocks
			32	Pre placement activities in VLSI Design
			33	Module Constraint types : Guide, Fence and Region
	7	Placement	34	Placement Steps in VLSI
	8	CTS	35	Clock Tree Constraints in VLSI
	9	STA	##	Setup and Hold violation
			##	Setup fixing Techniques
			##	Hold Fixing Techniques
			36	IO Interfece analysis: IO constraints on block level
	10	ECO	##	How to impliment ECO in Physical Design
			37	ECO flow in Physical Design
	11	Linux	##	Basics of sed commands
			##	Basics of awk command
			##	Basics of grep command
			38	50 Most usefull commands fro VLSI Engineers
	12	EDA Tools	39	Installation of Synopsys tools
			##	Installatio of MentorGraphics tools
			##	Installation of Cadence tools
			40	EDA tools in ASIC Industries
	13	Interview Section	41	Physical Design Interview Questions for 3 years experience , Question set - 8
			42	Physical Design Interview Questions : Question set -7
			43	Written Test Question for Physical Design Engineer: Question Set - 6
			44	Synthesis and Physical Design Interview Questions: Question Set -5
			45	Physical Verification Interview Questions : Question set - 4
			46	Physical Verification Interview Questions : Question set - 3
			47	Physical Verification Interview Questions : Question set - 2
			48	Logic Synthesis and Physical Design Interview Questions : Question set - 1
			49	Basic Dos and Don'ts for Freshers in VLSI Interview
	14	Books and Articles	50	Best 25 books on VLSI Design
			51	Top 5 books for Physical Design Engineer

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