Physical Design Interview Questions : Question set -7

 

Code: CDN5Y062021PD

Experience level: 5 Years

For Application Engineer

1. What are the major differences between 7nm and 12/14nm technology nodes?
2. What are the new DRC rules in the 7nm technology node?
3. What is the via-piller?
4. What is double patterning?
5. How many layers have double patterning in the 7nm node?
6. How tool performs placement steps?
7. Why do we perform scan chain reordering?
8. What is scan mode, why do we need that?
9. What is ECF (Early Clock Flow) flow?
10. What are the benefits of ECF flow?




11. Can you explain the CTS flow?
12. What are the low power techniques used in data and clock paths?
13. Where does the clock-gater use?
14. Have you built a custom clock tree?
15. What are the constraints you have given to the clock tree?
16. How did you solve max_trans violations in the clock path?
17. How to provide different clock tap points in H-Tree?
18. How many clocks were there in your block?
19. How were they related?
20. How did you analyze the clock domain crossing paths?
21. What is a lock-up latch and how does it helps in hold fixing?
22. What was the target skew in your block?
23. What value of skew you achieved?