Best 25 books on VLSI Design

In the previous article, Best 5 books have recommended for Physical Design Engineer. While writing that article it was very difficult to make many books out of the list. So I thought it will be better to write another article on the best 25 books for VLSI Design. This list starts from the basic level of books to the advance level of books. I have categories these books into 8 major categories. 

If you wish you buy any books, I have searched the bestseller, best edition and best price of these books and linked here. You can buy these books from these links through amazon. 

I. Basic Digital Electronics

1. Electronic Devices And Circuits Theory by Robert L. Boylestad 

The main content of this book is as follow:

1. Semiconductor Diodes
2. Diode applications
3. Bipolar Junction Transistor
4. DC Biasing - BJT
5. BJT AC Analysis
6. Field-Effect Transistors
7. FET Biasing 
8. FET amplifier
9. BJT and JFET Frequency response
10. Operational Amplifiers
11. OP-Amp applications 
12. Power Amplifiers
13. Linear Digital ICs
14. Feedback and Oscillator Circuits
15. Power Supply (Voltage Regulators)
16. Other Two Terminals Devices
17. PNPN and other devices

2. Digital Design with an Introduction to the Verilog HDL by M. Morris Mano 

The main content of this book is as follow:

1. Binary Systems
2. Boolean Algebra and Logic Gates
3. Simplification of Boolean Functions
4. Combinational Logic
5. MSI and PLD Components
6. Synchronous Sequential Logic
7. Registers, Counters and The Memory Units
8. Algorithm State Machines (ASM)
9. Asynchronous Sequential Logic
10. Digital Integrated Circuits
11. Laboratory Experiments
12. Standard Graphics Symbols

II. Verilog HDL and SystemVerilog

3. Verilog HDL by Samir Palnitkar 

The main content of this book is as follow:

1 Overview of Digital Design with Verilog HDL 

2 Hierarchical Modeling Concepts 

3 Basic Concepts 

4 Modules and Ports 

5 Gate-Level Modeling 

6 Dataflow Modeling 

7 Behavioral Modeling 

8 Tasks and Functions 

9 Useful Modeling Techniques 

10 Timing and Delays 

11 Switch-Level Modeling 

12 User-Defined Primitives 

13 Programming Language Interface 

14 Logic Synthesis with Verilog HDL

4. FPGA Prototyping by Verilog Examples by Pong P. Chu 

The main content of this book is as follow:

1. Gate-Level Combinational Circuits
2. Overview of FPGA and EDA software
3. RTL combinational circuit
4. Regular Sequential Circuit
5. FSM
6. FSMD
7. Selected Topics of Verilog
8. UART
9. PS2 Keyboard
10. PS2 Mouse
11. External SRAM
12. Xilinx Spartan-3 Specific Memory
13. VGA Controller -1: Graphics
14. VGA Controller-II: Text
15. PicoBlaze Overview
16. PicoBlaze Assembly Code Development
17. PicoBlaze I/O Interface
18. PicoBlaze Interrupt Interface
19. Simple Verilog Templates

5. SystemVerilog for Verification by Chris Spear 

The main content of this book is as follow:

1. Verification Guidelines
2. Data Types Procedural Statements and Routines
3. Connecting the Testbench and Design
4. Basic OOP
5. Randomization Threads and Interprocess Communication
6. Advanced OOP and Testbench Guidelines
7. Functional Coverage
8. Advanced Interfaces
9. A Complete SystemVerilog Testbench
10. Interfacing with C/C++

III. Semiconductor Devices

6. Solid State Electronic Devices by Streetman and Banerjee

7. VLSI Technology by S. M. SZE

8. The MOS Transistor by Yanish Tsividis

IV. Fabrication Technologies

9. The Science and Engineering of Microelectronic Fabrication by Stephen A Campbell 

9.a. Fundamental of Semiconductor Fabrication by S M SZE

The main content of this book is as follow:

1. Introduction
2. Crystal Growth
3. Silicon Oxidation
4. Photolithography
5. Etching
6. Diffusion
7. Ion Implantation
8. Film Deposition
9. Process Integration
10. IC Manufacturing
11. Future Trends and Challenges

V. Analog Design

10. Design of Analog CMOS Integrated Circuits by Behzad Razavi

11. Microelectronic Circuit Theory and Application by Sedra and Smith

12. CMOS Circuit Design, Layout and Simulation by R. Jacob Baker

VI. Digital Design

13. CMOS Digital Integrated Circuit by Sung-Mo Kang and Yusuf Leblebici

14. Digital Integrated Circuit by Rabaey

15. CMOS VLSI Design by Neil H E Weste 

VII. Low Power Design

16. Low Power CMOS VLSI Circuit Design by Kaushik Roy 

17. Practical Low Power VLSI Design by Gary K. Yeap

VIII. Advance Books

18. Static Timing Analysis For Nanometer Design by J Bhaskar 

The main content of this book is as follow:

1. CHAPTER 1: Introduction
2. CHAPTER 2: STA Concepts
3. CHAPTER 3: Standard Cell Library
4. CHAPTER 4: Interconnect Parasitics
5. CHAPTER 5: Delay Calculation
6. CHAPTER 6: Crosstalk and Noise
7. CHAPTER 7: Configuring the STA Environment
8. CHAPTER 8: Timing Verification
9. CHAPTER 9: Interface Analysis
10. CHAPTER 10: Robust Verification

19. Constraining Design for Synthesis and Timing Analysis by Sridhar Gangadharan  

                        

20. Advance ASIC Chip Synthesis by Himanshu Bhatnagar 

The main content of this book is as follow:

1. ASIC DESIGN METHODOLOGY TUTORIAL
2. BASIC CONCEPTS
3. SYNOPSYS TECHNOLOGY LIBRARY
4. PARTITIONING AND CODING STYLES
5. CONSTRAINING DESIGNS
6. OPTIMIZING DESIGNS
7. DESIGN FOR TEST
8. LINKS TO LAYOUT & POST LAYOUT OPT
9. PHYSICAL SYNTHESIS
10. SDF GENERATION
11. PRIMETIME BASICS
12. STATIC TIMING ANALYSIS

21. Physical Design Essentials by Khosrow Golshan

The main content of this book is as follow:

Chapter 1: Libraries 

1.1 Standard Cells 1.4 Library Characterization

Chapter 2: Floorplanning

2.1 Technology File 2.3 Design Constraints

2.4 Design Planning

2.5 Pad Placement

2.6 Power Planning

2.7 Macro Placement

Chapter 3: Placement 

3.1 Global Placement 3.2 Detail Placement

3.3 Clock Tree Synthesis

3.4 Power Analysis

Chapter 4: Routing 

4.1 Special Routing

4.2 Global Routing

4.3 Detail Routing

4.4 Extraction

Chapter 5: Verification

5.1 Functional Verification 5.2 Timing Verification

5.3 Physical Verification

Chapter 6: Testing

6.1 Functional Test

6.2 Scan Test 6.3 Boundary Scan Test

6.4 Fault Detection

6.5 Parametric Test

6.8 Memory Test

22. Algorithm for VLSI Physical Design Automation by Naveed Sherwani

23. VLSI Design Methodology Development by Thomas Dillinger

24. Characterization and Modeling of Digital Circuits by Rohit Sharma

25. The Art of Timing Closure by Khosrow Golshan

        

Hope this article will help you to decide which are the best books available and which you need to read. 

Thank you!

Top 5 books for Physical Design Engineer

If you want to enhance your understanding and grow in any field, books can be your best buddy. Reading good books is a proven way to enhance understanding and develop depth knowledge of any domain. So I would like to say, the semiconductor industry is not an exception to this trend. If you want to develop your deep understanding, the working experience and learnings are not sufficient, you must have to develop the habit of reading too.

The semiconductor industry is a very fast-moving industry in terms of technology development. We are witness of many such developments in recent years like many lower nodes, multiple patterning, DUV to EUV and many more. Many of the basic concepts you need to read and understand from books, many can be read from recent journals/conference publication and articles. There are many good books in this area which are quite popular in the semiconductor professional and researcher community. In this article, I would like to recommend the top 5 books which every Physical design engineer must-read.

If you wish you buy any books, I have searched the bestseller, best edition and best price of these books and linked here. You can buy these books from these links through amazon. 

1. "Static Timing Analysis for Nanometer Designs" by J. Bhashkar and Rakesh Chadha 

Buy Now

In this list, my first recommendation would be a very popular book titled "Static Timing Analysis for Nanometer Designs" by J. Bhashkar and Rakesh Chadha. This books basically deals all the Static timing-related concepts and many SDC commands. Beyond the STA there are many more good concepts related to standard cells timing and clock has covered and explained very well.

The main content of this book is as follow:

CHAPTER 1: Introduction 
CHAPTER 2: STA Concepts
CHAPTER 3: Standard Cell Library
CHAPTER 4: Interconnect Parasitics
CHAPTER 5: Delay Calculation
CHAPTER 6: Crosstalk and Noise
CHAPTER 7: Configuring the STA Environment
CHAPTER 8: Timing Verification
CHAPTER 9: Interface Analysis

CHAPTER 10: Robust Verification

2. "Physical Design Essentials: An ASIC Design Implementation Perspective" by Khoshrow Golshan

Buy Now

2nd book which I recommend is "Physical Design Essentials" written by Khoshrow Golshan. This book is very good for all freshers who are planning to enter the Physical design world. This book explains the Industries common ASIC Design flow, Floorplan, Placement, CTS, Routing, Verification and Testing. The main content of this book is as follow:

Chapter 1: Libraries

1.1 Standard Cells 1.4 Library Characterization

Chapter 2: Floorplanning

2.1 Technology File 2.3 Design Constraints
2.4 Design Planning
2.5 Pad Placement
2.6 Power Planning
2.7 Macro Placement

Chapter 3: Placement

3.1 Global Placement 3.2 Detail Placement
3.3 Clock Tree Synthesis
3.4 Power Analysis

Chapter 4: Routing

4.1 Special Routing
4.2 Global Routing
4.3 Detail Routing
4.4 Extraction

Chapter 5: Verification

5.1 Functional Verification 5.2 Timing Verification
5.3 Physical Verification

Chapter 6: Testing

6.1 Functional Test

6.2 Scan Test 6.3 Boundary Scan Test

6.4 Fault Detection

6.5 Parametric Test

6.8 Memory Test

  

 3. "CMOS Digital Integrated Circuits Analysis and Design" by Sung-Mo Kang and Yusuf Leblebici

Buy Now

This book is the most favourite book in the academics. The book starts with the basic of MOS Transistors, Scaling, Modeling of MOSFET, CMOS Inverter characteristics, combinational and Sequential logic, SRAM design then Low power CMOS logic circuits. The contents of this book are as follow:

1 INTRODUCTION 2 FABRICATION OF MOSFETs
3 MOS TRANSISTOR
4 MODELING OF MOS TRANSISTORS USING SPICE
5 MOS INVERTERS: STATIC CHARACTERISTICS 

6 MOS INVERTERS: SWITCHING CHARACTERISTICS AND INTERCONNECT EFFECTS
7 COMBINATIONAL MOS LOGIC CIRCUITS 8 SEQUENTIAL MOS LOGIC CIRCUITS
9 DYNAMIC LOGIC CIRCUITS
10 SEMICONDUCTOR MEMORIES
11 LOW-POWER CMOS LOGIC CIRCUITS
12 BiCMOS LOGIC CIRCUITS
13 CHIP INPUT AND OUTPUT (O) CIRCUITS
14 VLSI DESIGN METHODOLOGIES
15 DESIGN FOR MANUFACTURABILITY
16 DESIGN FOR TESTABILITY

4. "The MOS Transistor" by Yanish Tsiwidis

 

Buy Now

This book is one the standard book on MOS transistors in Academics as well as industry. My personal feeling in that the writer Yanish Tswidis is the God of MOS Transistors.

The first image is shown is the Indian 3rd edition and I would like to recommend you if you have not read this book till now, you must read this. You can buy this book from the following link.

A course on this book is also available on the Coursera website.

5. "Verilog HDL A Guide to Digital Design and Synthesis" by Samir Palnitkar

Buy Now

This book is a very standard book to learn Verilog HDL and quite popular. You must go through this book either you are working on RTL design or not, but one must has an understanding of RTL codes.  The contents of this book are as follow:

1 Overview of Digital Design with Verilog HDL
2 Hierarchical Modeling Concepts
3 Basic Concepts
4 Modules and Ports
5 Gate-Level Modeling
6 Dataflow Modeling
7 Behavioral Modeling
8 Tasks and Functions
9 Useful Modeling Techniques
10 Timing and Delays
11 Switch-Level Modeling
12 User-Defined Primitives
13 Programming Language Interface
14 Logic Synthesis with Verilog HDL

This was a very short list of books, actually, my favourite list is quite long. You might feel that I have missed some important books. Yes, that's right and I will cover all those in another article. You can comment on the name of your most favourite book. 

Thank You!

Physical Verification Interview Questions : Question set - 4

 

Code: QLCM2Y062020PV

General Questions

1. What are lambda based design rules?
2. What is nm in 10nm technology node?
3. Do you know about under bum density?
4. Any prior experience of PnR?
5. How do you import design in PnR?
6. Why ID layers have been given in lower nodes (10nm)?
7. Why nwell continuity is required?
8. Have you done scripting?
9. Can you write an algorithm?
10. What is drive strength?
11. Why the industry is moving towards lower technology nodes like 7nm or 5nm?
12. What are challenges seen in lower technology node?

Physical Only Cell

1. What is a tap cell?
2. What are the uses of tap cells?
3. What is Endcap or boundary cell?
4. How does halo cell avoid DRCs t boundary? What is there inside the halo cell that prevents DRCs ? How it is different from standard cells?
5. What difference it makes when you add halo cell in boundary instead of standard cell?
6. Why is the standard cell nwell bigger in size and slightly coming out of the standard cell? It is not so in halo cell.
7. Suppose a tap cell is covering 10um distance, then where should the next tap cell be placed in the same row?
8. How do you calculate the distance between tap cells in a row?

DRC

1. What kind of base DRCs have you encountered?
2. Have you seen DRCs between the standard cell and filler cell of the same height?
3. What is Endcap or boundary cell?
4. How did you solve DPT (double patterning)?
5. What metal DRC have you encountered?
6. What kind of via DRCs have you come across?
7. What will happen if GDSII has DRC unfixed and sent to Fab?
8. Is there any problem if the ID layers are interchanged?
9. Which ID layer is manufactured first?

LVS

1. Have you analyzed the LVS result or someone else analyzed the result and you fixed?
2. Apart from short and opens what errors have you seen in LVS and How did you resolve?
3. What kind of issues are seen in LVS?
4. What is priority errors in LVS? Could there be false violations?
5. Where does the tool start to calculate LVS from?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks, Karthik for sharing and helping people.

6.

11

Physical Verification Interview Questions : Question set - 3

 

Code: INTL2Y052020PV

Floorplan

1. What are the inputs for floorplan?
2. In order to make sure integration is DRC clean, what rules or guidelines need to be followed at the floorplan stage?
3. Can we abut macros on par boundary?
4. How will judge the congestion between two IPs during floorplan stage without actual routing being done?
5. Apart from IP alignment, what analysis have you done?
6. What do you check at the placement stage? 

Physical Only Cell

1. What are the types of physical only cells in the design?
2. In what stage are physical only cells placed in the design?
3. Why are different types of physical only cells needed in design?

Latch-up

1. Are you aware of latch-up in CMOS, can you elaborate?
2. Explain how the parasitics are formed?

Antenna Effect

1. What is the antenna effect?
2. How can antenna effect be solved?
3. Why metal jogging is done in the higher layer during antenna fixing?
4. Which diode is used as an antenna diode?
5. What parameters are considered while choosing the cutoff voltage of an antenna diode?
6. How do you decide the number of diodes that needs to inserted for the failing net?
7. On what basis have you inserted diodes?
8. If M12 is the highest metal in the design and it has antenna, how do you fix it?
9. Have you heard of nwell antenna?
10. Can power net have an antenna effect?
11. Can the antenna diode be placed in a different power from that of the affected cell?
12. What is the impact of placing the antenna diode on timing?
13. Where are the antenna diode terminals being connected?
14. Voltage or current that is causing the antenna effect?
15. How the gate area can be increased in antenna affected cell?
16. How are you adding the antenna in antenna affected cell?
17. What is the drive strength?
18. What is the W/L ratio?
19. Which layers are most susceptible to antenna violations, higher or lower layers? 
20. How do you handle antenna in clock net?

ECO Implementation

1. What are types of ECOs?
2. Where the ECOs generated and given to you or you prepared ECOs?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks Karthik for sharing and helping people.

Physical Verification Interview Questions : Question set - 2

Code: INTL2Y052020PV

General

1. What is done to solve congestion in lower and higher metal?
2. How cell spreading helps in routing congestion?
3. Cell spreading is done on what basis?
4. What is DFM and why is it needed?
5. What happens if DFM is not met?
6. What are the inputs to GDSII file?
7. What is crosstalk, Which checker is used to detect the crosstalk?
8. What is the difference between gate level netlist and layout netlist?
9. How does a MOSFET work?
10. What does the length of channel refer to?
11. Explain transfer characteristics of a CMOS Inverter.

DFM

1. Why Density needs to be maintained?
2. What kind of densities are there?
3. How do you know the density of each cell?
4. If there are 100 plus density windows, then how to fix it?
5. What happens if there are min or max density during fabrication?
6. Whats are the projects you have done related to synthesis and Physical Design?

DRC

1. What is DRC?
2. Will the design be clean if halos are places properly in design?
3. What are the types of DRC?

LVS

1. What is LVS What it checks for?
2. What are the inputs and outputs of LVS?
3. What are hierarchical shorts?
4. What are the inputs to generate the OASIS file?
5. What is the full form of OASIS?
6. What is the difference between ICC LVS and ICV LVS?
7. In what format does the tool calculate the LVS?

Post Credit: 

These questions are shared by Karthik K Umesh, one of our group member. Thanks Karthik for sharing and helping people.

Logic Synthesis and Physical Design Interview Questions : Question set - 1

 

Code: MDTK3Y062019PDSYN

1. Formal Introduction
2. Whats are the projects you have done related to synthesis and Physical Design?
3. Have you gone through Physical Design flow?
4. What is synthesis?
5. Whats are the inputs required for synthesis?
6. What does constraint files contain?
7.  What is a multicycle path?
8. What is a false path?
9. Why do we perform STA?
10. What is CTS?
11. Why do we perform Setup analysis?
12. How to fix setup violations?
13. What are the ways to fix the setup violations?
14. What is the clock skew?
15. Why CTS is done before Routing?
16. What is On-Chip Variation?
17. What is Antenna Effect?
18. What is library setup and hold time for a flip flop?
19. Why there is a setup time requirements for a flip flop?
20. Why Hold time required for a flip flop?
21. What is the temperature Inversion?
22. How does the threshold voltage vary with temperature?
23. How does mobility vary with temperature?
24. Do you have any questions for me?

Basic Dos and Don'ts for Freshers in VLSI Interview

Hello Guys,

As you all know that the entry in the VLSI Industry is not easy for freshers, and it becomes more difficult especially if you don't belong from tier-1 institutes of India. But keep good hopes always with you, people who are eligible, definitely get chance. So here important thing which I want to tell you is If you get an interview call, convert this rare opportunity into the offer later. And for freshers, believe me, what matters most is to start the first job irrespective of a big or small company. Once you are in the industry and working well, you can switch any company later. 

So, here are some Dos and Don'ts which a fresher's must follow during the interview. Never take too much pressure on the interview, but at the same time don't be ignorant. Your result will be determined on the basis of what you answer in the interview not what you know and understand. So being presentable and prepared matters most. 

Dos:

1. Choose the best environment:

If the interview is telephonic, you must choose a place where the network of your mobile is good, avoid any surrounding noise and use the best quality earphone. In a telephonic interview, your audio quality is a very important factor during the call. In case of the video call, make sure for the good bandwidth and audio/microphone connectivity and join the virtual meeting room on time. 

2. Be honest with your CV:

In fresher's interview, interviewers generally ask a few questions related to your CV only. So you must be aware whatever you have written in your CV and proper justification should be there if any questions arise from your CV. Be prepared and honest with your answers.

3. Think before answer:

Listen to the interviewer very carefully, take a small pause before answering if required and then answer. Many time your next question will come based on your current answer, so try to drive the interviewer in the right direction. 

4. Keep Answers short

Always try to keep your answer shorts, more you elaborate, more chances of mistakes. And some time interviewers are not interested to listen to the thing which he has not asked.

5. Answer to the point only

Always try to give the answer to the point. If you are not aware of the question, It's better to say Sorry and move to the next question instead of irrelevant answers. 

6. Be specific

If any question comes from your project/thesis be very specific, and tell them the exact problem/issue and how you solved that instead of giving a long theoretical answer. In the interview, your practical experience matters most than the general approach. But If any question comes to test your theoretical understanding then you may use a general concept for the explanation.

Don'ts:

1. Never rush to answer:

Sometimes a very well known question comes for which candidate is well prepared, so they start answering even before the interviewer complete the question. Avoid this thing, and wait for the completion of question. There may be some twist in the last part of the question.

2. Avoid criticism:

Sometimes questions come, like why do you want to join/work in a particular area, then never criticise the other domain, Just show your interest for which you have appeared in the interview 

3. Avoid exaggeration:

Never exaggerate any topic while answering a question, the best way is keep your answer short and to the point only.

Thank you!