In this article, we will discuss a widely used and very popular file used for data exchange from one EDA tool to another tool. Yes, we are going to discuss the Design Exchange Format or DEF file which is having extension .def. In this article, we will discuss the use of the def file, what information this file contains and how the information is arranged in various sections. We will also discuss how can we generate this file.
Introduction:
DEF file is used to represent the Physical layout of an Integrated Circuit (IC) in ASCII format. A DEF file is strongly connected with the Library Exchange Format (LEF) file. So both files needed for a correct display of physical design. DEF file format was developed by Cadence Design System. Whenever we need to transfer the design database from one EDA tool to another EDA tool for further implementation or analysis, we use the DEF file to transfer the design data. For example IR analysis on PnR database or STA on PnR database we transfer the design database in form of DEF file.
A DEF file contains the design-specific information of the circuit and it is a representation of the design at any point during the physical design. DEF conveys logical design data and physical design data.
Logical design data includes internal connectivity (represented by netlist), group information and physical constraints. Physical data includes placement location and orientation of components and routing geometry.
Sections:
A standard DEF file contains mainly following sections and order of statement is also important.
Here we will take a sample DEF file to describe the various sections of the file.
Header statement:
Figure-1: Header part of DEF file
In header part, version of DEF, Design name, Technology name, Units and Dia area are mentioned.
ROW statement:
Syntax:[ROW rowName
siteName
origX
origY
siteOrient [DO numX
BY numY
[STEP
stepX
stepY]] [+ PROPERTY {propName
propVal}
...] ... ;] ...
Here is an example of row section of def file.
[ROW rowName siteName origX origY siteOrient [DO numX BY numY [STEP stepX stepY]] [+ PROPERTY {propName propVal} ...] ... ;] ...
Here is an example of row section of def file.
Figure-2: Row statement in DEF file
rowName: Specifies the row name for this row.
siteName : Specify the LEF site to use for the row
origX origY : Specify the location of first site in the row
siteOrientation : Specifies the orientation of all sites in the row
Do numX BY numY :
•Specifies
the repeating set of sites that create
the row.•One
of value must be 1.
•If
numY
is 1, then row will be horizontalSTEP stepX stepY :
•Specifies
the spacing between sites in Horizontal
and Vertical row
Track statement:
Syntax:[TRACKS [{X | Y} start
DO numtracks
STEP space [LAYER layerName
...] ;] ...]
Example:Figure-3: Track statement in DEF file
Description:
{X | Y } start
•Specifies
the
direction
and location of first track defined
•X
indicates vertical lines and Y indicates horizontal line
•Start
is the X or Y coordinate of first line
Do numtracks
Specifies the number of tracks to create for the grid
STEP space:
•Specifies
the spacing between the tracksLAYER layerName
•Specifies
the routing layer used for this track
•We
can specify more than one layer
GCell Grid statement:
Syntax:[GCELLGRID {X start
DO numColumns+1
STEP space} ... {Y start
DO numRows+1
STEP space
;}
...]
Example:
Figure-4: Gcell statement in DEF file
Description:
{X | Y } start
:
•Specifies
the
location
of first vertical (x) and first horizontal (y) trackDo numColumns+1 :
Do numRows+1 :
•Specifies the number of columns or rows in the gridSTEP space:
•Specifies
the spacing between the tracks
Via statement:
Example:Figure-5: Via statement in DEF file
Description:All vias consist of shapes on three
Layers
1.A cut
layer
2.Two routing
(or masterslice)
layers that connect through that cut layer
NDR statement:
Syntax:NONDEFAULTRULES
numRules
;
{- ruleName
[+
HARDSPACING]
{+
LAYER layerName
WIDTH
minWidth
[DIAGWIDTH
diagWidth]
[SPACING
minSpacing]
[WIREEXT
wireExt]
} ...
[+
VIA viaName] ...
[+
VIARULE viaRuleName] ...
[+
MINCUTS cutLayerName
numCuts] ...
[+
PROPERTY {propName
propVal}
...] ...
;}
...
END
NONDEFAULTRULES
Example:Figure-6: NDR in DEF file
Description:•It
defines any nondefault
rules used in this design that are not specified in the LEF file.
•This
section can
also contain the default rule and LEF nondefault rule definitions for reference.
rowName: Specifies the row name for this row.
siteName : Specify the LEF site to use for the row
origX origY : Specify the location of first site in the row
siteOrientation : Specifies the orientation of all sites in the row
Do numX BY numY :
STEP stepX stepY :
Track statement:
[TRACKS [{X | Y} start DO numtracks STEP space [LAYER layerName ...] ;] ...]
Description:
{X | Y } start
Do numtracks
Specifies the number of tracks to create for the grid
STEP space:
LAYER layerName
[GCELLGRID {X start DO numColumns+1 STEP space} ... {Y start DO numRows+1 STEP space ;} ...]
Example:
Figure-4: Gcell statement in DEF file |
Description:
{X | Y } start :
Do numColumns+1 :
Do numRows+1 :
STEP space:
Via statement:
All vias consist of shapes on three Layers
NONDEFAULTRULES numRules ;
{- ruleName
[+ HARDSPACING]
{+ LAYER layerName
WIDTH minWidth
[DIAGWIDTH diagWidth]
[SPACING minSpacing]
[WIREEXT wireExt]
} ...
[+ VIA viaName] ...
[+ VIARULE viaRuleName] ...
[+ MINCUTS cutLayerName numCuts] ...
[+ PROPERTY {propName propVal} ...] ...
;} ...
END NONDEFAULTRULES
Component section:
•It
defines
design
components, their location, and associated attributes
•A
big section in DEF file
Syntax:COMPONENTS numComps
;
[– compName
modelName
[+ EEQMASTER macroName]
[+ SOURCE {NETLIST | DIST | USER |
TIMING}]
[+ {FIXED pt orient |
COVER pt
orient |
PLACED pt
orient
| UNPLACED} ]
[+ HALO [SOFT] left
bottom right top]
[+ ROUTEHALO haloDist
minLayer
maxLayer]
[+ WEIGHT weight]
[+ REGION regionName]
[+ PROPERTY {propName
propVal}
...]...
;] ...
END COMPONENTS
COMPONENTS numComps ;
[– compName modelName
[+ EEQMASTER macroName]
[+ SOURCE {NETLIST | DIST | USER | TIMING}]
[+ {FIXED pt orient | COVER pt orient | PLACED pt orient
| UNPLACED} ]
[+ HALO [SOFT] left bottom right top]
[+ ROUTEHALO haloDist minLayer maxLayer]
[+ WEIGHT weight]
[+ REGION regionName]
[+ PROPERTY {propName propVal} ...]...
;] ...
END COMPONENTS
Example:
Figure-7: Component section in DEF file
Pin section:•It
defines external
pins
•Each
pin
definition assigns a pin name for the external pin and
associates the
pin name with a corresponding internal net name
•The
pin
name and the net name can
be the same.
Example:Blockage section:
•Defines
placement
and routing blockages in the design
•PUSHDOWN
: Specifies that the blockage was pushed down into the block from
the top
level of the designExample:Figure-9: Blockage section in DEF file
Special net section:
Syntax:[SPECIALNETS numNets
;
[– netName
[ ( {compName
pinName
| PIN
pinName} [+
SYNTHESIZED] ) ] ...
[+ VOLTAGE volts]
[specialWiring] ...
[+ SOURCE {DIST | NETLIST | TIMING |
USER}]
[+ FIXEDBUMP]
[+ ORIGINAL netName]
[+ USE {ANALOG | CLOCK | GROUND | POWER |
RESET | SCAN | SIGNAL | TIEOFF}]
[+ PATTERN {BALANCED | STEINER | TRUNK |
WIREDLOGIC}]
[+ ESTCAP wireCapacitance]
[+ WEIGHT weight]
[+ PROPERTY {propName
propVal}
...] ...
;] ...
END SPECIALNETS]
Example:Figure-10: Special net section in DEF file
Net section:
Syntax:NETS numNets
;
[– { netName
[ ( {compName
pinName
| PIN
pinName} [+
SYNTHESIZED] ) ] ...
| MUSTJOIN ( compName
pinName
) }
[+ SHIELDNET shieldNetName
] ...
[+ VPIN vpinName
[LAYER
layerName] pt
pt
[PLACED pt orient |
FIXED pt
orient |
COVER pt
orient] ]
...
[+ SUBNET subnetName
[ ( {compName
pinName
| PIN
pinName
|
VPIN vpinName} ) ]
...
[NONDEFAULTRULE rulename]
[regularWiring]
...] ...
[+ XTALK class]
[+ NONDEFAULTRULE ruleName]
[regularWiring] ...
[+ SOURCE {DIST | NETLIST | TEST | TIMING
| USER}]
[+ FIXEDBUMP]
[+ FREQUENCY frequency]
[+ ORIGINAL netName]
[+ USE {ANALOG | CLOCK | GROUND | POWER |
RESET | SCAN | SIGNAL
| TIEOFF}]
[+ PATTERN {BALANCED | STEINER | TRUNK |
WIREDLOGIC}]
[+ ESTCAP wireCapacitance]
[+ WEIGHT weight]
[+ PROPERTY {propName
propVal}
...] ...
;] ...
END NETS
Example:Figure-11: Net section of DEF file
[SPECIALNETS numNets ;
[– netName
[ ( {compName pinName | PIN pinName} [+ SYNTHESIZED] ) ] ...
[+ VOLTAGE volts]
[specialWiring] ...
[+ SOURCE {DIST | NETLIST | TIMING | USER}]
[+ FIXEDBUMP]
[+ ORIGINAL netName]
[+ USE {ANALOG | CLOCK | GROUND | POWER | RESET | SCAN | SIGNAL | TIEOFF}]
[+ PATTERN {BALANCED | STEINER | TRUNK | WIREDLOGIC}]
[+ ESTCAP wireCapacitance]
[+ WEIGHT weight]
[+ PROPERTY {propName propVal} ...] ...
;] ...
END SPECIALNETS]
NETS numNets ;
[– { netName
[ ( {compName pinName | PIN pinName} [+ SYNTHESIZED] ) ] ...
| MUSTJOIN ( compName pinName ) }
[+ SHIELDNET shieldNetName ] ...
[+ VPIN vpinName [LAYER layerName] pt pt
[PLACED pt orient | FIXED pt orient | COVER pt orient] ] ...
[+ SUBNET subnetName
[ ( {compName pinName | PIN pinName | VPIN vpinName} ) ] ...
[NONDEFAULTRULE rulename]
[regularWiring] ...] ...
[+ XTALK class]
[+ NONDEFAULTRULE ruleName]
[regularWiring] ...
[+ SOURCE {DIST | NETLIST | TEST | TIMING | USER}]
[+ FIXEDBUMP]
[+ FREQUENCY frequency]
[+ ORIGINAL netName]
[+ USE {ANALOG | CLOCK | GROUND | POWER | RESET | SCAN | SIGNAL
| TIEOFF}]
[+ PATTERN {BALANCED | STEINER | TRUNK | WIREDLOGIC}]
[+ ESTCAP wireCapacitance]
[+ WEIGHT weight]
[+ PROPERTY {propName propVal} ...] ...
;] ...
END NETS
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