Code: ALTRN0Y112020PD
Some companies take a written test sometimes to shortlist the candidates before the interview process. This is a common process if the applicants are large in numbers. In such written test, the format is MCQ and some short questions.
We are very thankful to one of our follower who has appeared in this test and shared these questions based on memory. The purpose of sharing this question is only to provide the right guidance to the candidate who is going to appear in such a written test. I would encourage all the freshers to practice these question for their future test/Interview. I would also encourage to find the answer to these question either by own. There is no sense of proving the answer to these questions here. But if someone finds any question really difficult to solve and open discussion in the comment section.
1. Hold slack equation
2. Setup slack equation
3. When did hold analysis depends on the frequency of the clock
a) half cycle pathb) single cycle pathC) multicycle pathd) it never depends
4. While doing OCV which things are considered for setup analysis
a) max launch path delay and min capture path delayb) min launch path delay and max capture path delayc) max launch and capture path delayd) min launch and capture path delay
5. How to fix EM effect
a) decreasing the space between metal layersb) decreasing strapsc) increasing drive strength of the driverd) increasing space between metal layers
6. Why do we add tap cells
a) to maintain well continuityb) to prevent latch upc) to prevent DRC'sd) all of the above
7. Why do we add metal fillers
a) to ensure etching properlyb) to ensure density issuesc) to increase the area of the chipd)to ensure well continuity
8. If the schematic has 11 and layout is 10 nets then, what might be reason
a) opensb) shortsc) ERCd) all of the above
9. Numerical problem related to finding clock frequency
10. Numerical problem related to finding slack
11. High positive skew leads to
a) setup violationb) hold violationc) DRcsd) all of the above
12. In VLSI Design, CMP stands for?
13. Numerical problem to find setup slack
14. Nand and Nor gate logic diagram SOP forms
15. Setup uncertainty increases from placement to CTs
a) trueb) falsec) based on SDCd) based on clock frequency
16. Only clearing LVS leads to the proper functioning of the chip
a) trueb) false
17. Numerical problem related to reg to reg data path delay calculation
18. A CMOS circuit consumes only a significant amount of power during
a) static stateb) when coolingc) when warmingd) all of the above
19. Routing congestion depends on which factors
a) ratio of required layers and available layersb) ratio of available and requiredc) depending on availability of metalayersd) none of the above
20. Question related to ground bounce, power bounce and glitch
21. Value of threshold voltage depends on
a) doping concentrationb)distance between source and drainc) temperatured) all of the above
22. Why we reorder scan chains during placement stage?
23. For multi-voltage blocks which power cells are used
a) isolation cellsb) retention cellsc) level shiftersd) all
24. Which configuration is more preferable for floorplan
a) double BACK + channel width spacingb) without double back + channel width spacingc) double back + row alignmentd) none of the above
25. Concept of fixing time violations by adjusting clock arrival times at the registers in the preCTS stage is called
a) time borrowingb) managing skewc) maintaining timingd) none of the above
26. While calculating standard cell utilization what are all will be considered
a) macro + blockage + standard cell (area)b) macro + blockage (area)c) macro + physical cells + standard cells (area)d) all of the above
27. RV checks Are needed for
28. Inputs for LVS
a) spice + netlist + rule deckb) spice + rule deck + lib filesc) OASIS + netlist + libd) none of the above
29. Via3 will connect which of the following metal layers
a) 1 and 3b) 2 and 3c) 3 and 4d) none
30. A 4-bit modulo 16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50 ns. The max. clock frequency that can be used is equal to
31. A pulse has a period of 15 ms. Its frequency is
32. A 8-bit successive approximation ADC has a full-scale reading of 2.55 volts and its conversion time for an analog input of 1 volt is 20 µs. The conversion time for a 2 volts input will be?
33 . How many binary numbers are required to represent a decimal number 748?
34. DRC is used to
a)to ensure chip fabricationb)to ensure chip doesn't get heatedc)to verify parasitics on chipd) all of these
35. Antenna diodes are used for
a) to protect the gateb) protect VDD and VSSc) to protect the substrated) all of the above
36. Buffers are added to
a) to fix timing violationsb) to fix DRCc) to fix parasitic valuesd) all
37. Metal pitch and metal spacing are the same
TrueFalse
38. What is the effect of high drive strength buffer when added in the long net
a) delay of net decreasesb) delay of net increasesc) delay doesn't effectd) none of the above
39. Cross talk glitch leads to
a)timing failureb) functional failurec) substrate failured)all of these
40. Programmable special cells used during ECO
a) gate array filler cellsb) filler cellsc) metal fillsd)decap cells
41. What is a physical cell?
a) cell which doesn't have any functionalityb) cell is not synthesizedc) cell which is inserted only in layoutd) all of the above
42. Power gating technique in low power is used to reduce
a)static powerb)leakage powerc)internal powerd) all of the above
43. Which of the following is not present in SDC
a) max capb) max transc) max current densityd) max fanout
44. The phenomenon associated with transistor switching when the gate voltage may appear less than the local ground potential
a) ground bounceb) supply bouncec) glitchD) none
45. Leakage recovery can be achieved through
a)Hvt to Svtb) Lvt to HvtC)Rvt to Lvt.d) svt to lvt
46. Which of the following must be fixed during physical design
a) floating inputsb) floating outputsC) floating metalsd) both b and c
47. Which slew value will be propagated to slew _out of slew _A is 100 ps and slew_B is 80ps for hold analysis
a) 80 psb) 100 psc) 20 plsd) 180 ps
48. A 16-bit modulo 16 ripple counter uses JK flops if propagation delay is 25 ns, the max frequency of the clock is
a) 25b) 10c) 2d) 16
49. Digital signals transmitted on a single conductor must be transmitted in
a) serialb) digitalC) slow speedd) none
50. In a certain digital waveform, the period is four times the pulse width, the duty cycle of the waveform will be?
51. Follow pin connections to the standard s are done in encounter through
a)z- routeb)s-routec)trail routed) nano- route
52.set Y[ ];
set Z[a,b,c];
lappend $Y,$Z;
What is the output
a) empty listb) [a b]c) [a b c]d) none
[ Note: If you find any question has typo error or wrong, comment for the correction.]
Thank you.
