Temperature Inversion in VLSI

If a simple question comes before you that "What will impact on the delay of a standard cell if temperature varies? " Are you going to answer straightforward the delay of the cell will increase with temperature OR The delay of the cell will decrease with temperature? If you are going with either of the above answers, Then you need to spare some moment in this article and understand the concept of Temperature Inversion.

Figure-1: Trend of cell delay with temperature

What is temperature inversion?

In general, as temperature increases, the delay of standard cells increases because of mobility degradation at higher temperatures. But in lower technology nodes the impact of temperature on the delay of the cell is inverse. In lower nodes, the delay of the cell decreases with an increase in temperature. So in the lower technology node, the effect of temperature on the delay of the cell is inverted and this effect is called the temperature inversion. The main reason behind this inversion is in the lower technology node, the effect of the threshold voltage is dominating over the mobility. 

So an appropriate answer to the above question could be we should answer this question with respect to the technology node. One can say that at the lower technology nodes as temperature increases the delay of cell decreases. Here lower technology node means the technology node below 65nm. Why part of this question is important, but we should wait if it is asked further. In the next part, we will learn why temperature inversion occurs.

Figure-2: Temperature inversion

The following section will explain in detail of factors affecting the delay of cells and their variation.

Reason for temperature inversion

The delay of a cell is simply the time required to charge/discharge the load capacitance. The charging and discharging time of the load capacitor depends on the drain current. If the drain current is high, it will take a lesser time to charge/discharge the load capacitor and so delay will be lesser and vice-versa. Now let's see the dependency of drain current Id.

The saturation current of MOSFET is,

The drain current Id is directly proportional to the mobility of charge carriers. So as the temperature increases, the lattice scattering increases, and ultimately the mobility of the charge carrier decreases which leads to the decrease in drain current Id and so it increases in the delay of the cell. 

Now let's come to the second important factor, the term (Vgs - Vt) in the above equation is called overdrive voltage. There is a variation in threshold voltage with temperature as per the following equation,

As temperature increases, the threshold voltage decrease, and overdrive voltage increases. This overdrive voltage is more dominating in the lower technology node because in the lower technology node the Vgs and Vt are more closers and so a slight change in Vt will have more impact on overdrive voltage. But in a higher technology node since Vgs is much larger than Vt so a slight change in Vt not causes much change in overdrive voltage. Again the Id is proportional to the squire of overdrive voltage. So changes in overdrive voltage are further amplified and it is dominating over the mobility in lower technology node. 

In a nutshell, In a lower technology node, as temperature increases the threshold voltage decreases so overdrive voltage and drain current increase which leads decrease in cell delay. Here overdrive voltage is dominating over the mobility factor. But in higher technology nodes, overdrive voltage is not much dominating, and delay of the cell varies as per variation in carrier mobility and we have discussed as temperature increases mobility decreases and so drain current decreases which lead increase in cell delay. 

So There are two major factors that drive the variation in cell delay, mobility and overdrive voltage. In lower technology nodes overdrive voltage is more dominating which causes the temperature inversion effect.

Thank you.