EDA tools in ASIC Industry

  We have noticed that when a person enters into the ASIC industry, He/She comes across various EDA tools of different EDA companies.  It's natural for experienced professionals that the name of tools/company easily gets remembered, but for the freshers, they often forget the name because it's new for them. It has also been noticed that in interviews sometimes interviewers ask the tool's name on which candidate has worked just to get the idea that which areas they have explored. Although remembering the tool's name does not define the level of intelligence of the candidate but of course, if you are not able to tell the name of the tools on which you have worked, will not give a good impression before the interviewer. It is always good to keep some information beyond your initial experience. For example, one might have worked only one STA tool say primeTime, but it's good to know what are other tools being used in Industry. 

This article will let you know the major EDA tools which are being widely used in the ASIC industry for different purposes. Each tool has some specialty over others but that is not a part of this article. We are not going to compare them. Here we will learn the popular tools used in ASIC Industries for various purposes and their company name. 

Kidly note that there are only a handful of EDA companies exists in the industry because If we look over the history of EDA company, we will find that there are lots of mergers and acquisitions had happened in this sector in past. Many new companies have come with their new innovative tool in past but somehow those have been acquired by the big players of this sector, and finally, the number of major EDA companies in the industry is very handful namely Cadence Design System, Synopsys, Mentor Graphics (now Siemens) and few more.

 Here we will categorize the major tools and their vendor as per their utility. I request to my readers there are lots of updates going on, many new tools beings launched every year, Therefore if I missed something important keep adding those in the comments, I will keep updating the list.

	Purposes	Tool	company
	RTL Simulations	VCS	Synopsys
		Xcelium	Cadence Design System
		NC-Sim	Cadence Design System
		QuestaSim	Mentor Graphics (Now Siemens)
		ModelSim	Mentor Graphics (Now Siemens)
		ISE Simulator	Xilinx
		Incisive	Cadence Design System
	RTL Signoff	SpyGlass	Synopsys
		JasperGold	Cadence Design System
	Logic Synthesis	Fusion Compiler (RTL-to-GDSII solution)	Synopsys
		Design Compiler	Synopsy
		Genus Synthesis Solution	Cadence Design System
		RTL Compiler (upgraded to Genus)	Cadence Design System
	LEC	Conformal	Cadence Design System
		Formality	Synopsys
	Place and Route	Innovus	Cadence Design System
		IC Compiler (ICC)	Synopsys
		Encounter (upgraded to Innovus)	Cadence Design System
	RC Extraction	Quantus RC Extraction	Cadence Design System
		StarRC	Synopsys
	STA	primeTime	Synopsys
		Tempus	Cadence Design System
		Tweaker	Dorado (Now a part of Synopsys)
		Encounter Timing System (ETS)	Cadence Design System
	IR Analysis	Voltus	Cadence Design System
		RedHawk	Ansys
	Pyhsical Verification (Fill, DRC, LVS, Antenna, PERC)	Calibre	Mentor Graphics (Now Siemens)
		IC Validator	Synopsys
		Pegasus	Cadence Design System
		PVS (Physical Verification System)	Cadence Design System
	Power simulation	Jules	Cadence Design System

There are some other useful tools here.

	Tools	Used for	Company Name
	OrCAD	PCB Design, Digital Design	Cadence Design System
	Spectre	SPICE Simulation	Cadence Design System
	HSPICE	SPICE Simulation	Synopsys
	Virtuoso	Schematic and Layout Editor	Cadence Design System
	Custom Designer	Schematic and Layout Editor	Synopsys
	Abstract	Abstract generation (.lef)	Cadence Design System
	Custom Waveview	Waveform viewer of simulated result	Synopsys
	Sentaurus SDevice	Device Simulator	Synopsys
	Sentaurus SProcess	Processes editor	Synopsys
	Sentaurus Sedit	GUI of device editor	Synopsys
	Svisual	visual tool for device and waveform	Synopsys
	3D TCAD	3D Device simulation	Synopsys
	Silvaco TCAD	TCAD Tool	Silvaco
	ICCAP	Device characterization/Testing	KeySight
	Liberate	Library characterization (.lib)	Cadence Design System
	LT Spice	A free SPICE simulator	Linear Technology

Thank You! 

If you feel, Something important is missing from this list, feel free to comment.

ECO Flow in Physical Design

 The tapeout is the final stage of the physical design process which definitely gives a big mental relax to the entire team involved in the project. The process of sending a clean layout file in form of gds/oasis to the foundry for fabrication after passing all the checks set by the foundry is termed as tapeout. But before the tapeout there might be many sleepless nights which physical design engineers / Signoff engineers spend and close the design. There are many signoffs like physical signoff, timing signoff and IR signoff which we need to get a closer state after which our layout is ready to send the foundry. And all these final achievements are done in the ECO (Engineering Change Order) phase. In this article, we will discuss the various aspects of the ECO cycle and how it works

.

ECO Phase:

ECO phase is the phase of design where we close all the signoff checks which remain open in the PnR stage. Generally in PnR we make timing, DRC and IR closable but the final closing is done in ECO phase. In ECO phase, we close the PnR implementation activities and solve all the open issue through the ECO only. But before entering the ECO stage we need to achieve good timing and DRC numbers and we must have confidence that all the open issues are closable in the ECO phase. In ECO phase we focus on closing each open issue, we generate ECO file and implement them on PnR tool incrementally. 

What is ECO cycle and how it works? 

In the ECO cycle, we perform various analysis one by one for every check which we need to close but not closed till PnR stage. There are specialized signoff tools that help us to analyze the issue and also suggest the changes we need to do in order to close the issue. The suggested change is captured in an eco file. 

Once we generate the ECO file for the fixes, we implement that on the PnR database on which we have performed the analysis. After the implementation of ECO file, we save the updated database which we carry forward for the next ECO generation and implementation. We repeat this ECO cycle for every open issue and close one by one all issues. There are chances that we might need multiple ECO cycle to close a single issue. 

ECO Cycles

So basically there are the following steps in each ECO cycle.

1. Analysis of an issue on the latest database
2. ECO generation for fixing the issue
3. ECO Implementation on the analyzed database
4. Save the database after ECO implementation for the next ECO cycle

Signoff Tools

Signoff tools are very specialized tools to perform the analysis for a particular issue thoroughly and also have the capability to generate the ECO file for the fixes.  We have various types of signoff tools as per the issue like timing signoff tool, Physical Signoff tool and IR signoff tools. Some of the popular signoff tools are as bellow.

Timing Signoff: 

1. PrimeTime or PT (of Synopsys)
2. Tempus (of Cadence Design Systems)
3. Tweaker (of Dorado, now a part of Synopsys)

Physical verification signoff tools:

1. Calibre (of Mentorgaphics now a part of Siemens)
2. IC Verification or ICV (of Synopsys)

IR Signoff Tools:

1. Redhawk (of Ansys)
2. Voltus (of Cadence Design Systems) 

ECO file

ECO file contains a series of changes required in the form of PnR tool command for fixing the issue. Based on the analysis, sometimes we generate the eco file from the signoff tool itself or sometimes we create our own eco file. 

For example, to fix the setup timing, we need to upsize the combinational cells or need to convert them to lower vt cells. In the case of a few hundred violating paths, these conversions of cells might be in thousands or more. So signoff tool will generate commands for each cell that need to be changed and write in a file that we call eco file. Later we source these file in PnR tool followed by refine placement and eco route. 

ECO Implementation

Once we have the solution of any issue in the form of ECO file, we need to load the database which was used to generate the ECO file and source the eco file. ECO implementation is generally done in the batch mode of the tool. We need to delete the fillers before sourcing the eco file. Once the eco file is sourced, all the required changes is done. Now there might be a change in the size of cells or addition/deletion of some cells so we need to do refine placement to followed by the eco route. These two steps will take care of any overlap of cells and routing of cells. The updated database need to be saved for next stage of ECO or the final database in case of all issues are fixed.

Thanks.

Floorplan Strategies for Macro Dominating Blocks

 A physical design engineer's main focus is to achieve a decent Quality of Result (QoR) and optimized Power Performance and Area (PPA). The start of this journey begins with the Floorplan steps. What will you achieve at the end of PnR is depends on how good your floorplan is. In case of a macro dominating block, the importance of quality floorplan is quite more. To achieve a good floorplan in a macro dominating block, it might take several iterations and also requires good experience. A detailed analysis of data flow, hierarchy, macro to input-output pins connection, logical depth and many more factors which need to understand and analyzed thoroughly to produce a good floorplan. In this article, we will discuss some of the basic rules on which are helpful to produce a good floorplan and so good QoR.  

There are some basic rules of macro placement which help to produce a good floorplan. There are many things which can be analyzed only after the first cut of floorplan result and macro placement can be improved in a few iterations in macro dominating blocks. There are some standard rules which help to achieve a good floorplan.

• Grouping of macros as per hierarchy

• Analysis of  macro to input/output pins connection  

• Logical depth analysis among macros and macros to Input/Output pin

• Maximizing the core area

• Avoid notch formation

• Channel spacing 

• Macro abbutment

• IO pins to macro spacing

• Halo over macros

• Routing blockage over macros

• Partial placement blockage in the macro channels and macro to io pins region

Above rules are the standard floorplan rules which generally people use as a thumb rule for better and timing and congestion results. Here it is important to understand that a where a well-planed floorplan can result in god timing and congestion result at the same time if the floorplan is not well planned could result in high congestion and high WNS/TNS/FEPs (Worst Negative Slack / Total Negative Slack / Failing End Points). So It is very important to follow the standard practice of macro placement to avoid high congestion and bad timings. 

Grouping of macros as per hierarchy

In a hierarchical design, macros must be placed as per their group in the hierarchy.  We can highlight the macros with different clours as per their group for better visibility of macro groups. PnR tools provide the option to see the macros and standard cells as per their hierarchy. For Innovus GUI this can be explored as Design Browser --> Modules

We can further visualize the group size and roughly estimate the required area for any particular group and place them in a better way after one-time placement is done. In a macro dominating block the macro count could be several hundred and the group could also be large. A sample picture has shown bellow. 

Macro Grouping

Design Browser in Innovus

Analysis of macro to Input/Output pin connections

Generally, we place the macros near to their io pins and if the logic level is only one than we can not put macro away from the pins to avoid in2reg or reg2out timing violation. So we need to check fanin and fanout of macro and try to place them near the connected pins.  

Logical depth analysis among macros and macros to Input/Output pins

Inside the groups of macro, the macro order must be as per their logical connection. Macro directly talking to each other should be placed together. Similarly, if two groups of macros have a logical connection with one register (only one level) we can not place them far away. But yes if two groups of a macro taking each other with logic level 3 or 4 or more, we can place them relatively apart from each other.

Maximize the core area

We always try to maximize the core area so that standard cells get more room for placement. If there are more rooms for placement there will be less chance of congestion and ultimately shorts. Generally, we try to place all the macro near the core boundary and try to maximize the centre area for the standard cells. 

Avoid notch formation

Notch area is not utilised effectively, so it will increase the placement density of the core and will rise the congestion. We always keep in mind while macro placement that notch should not be formed while macro placement especially in the case where the macro count is high and the placement density is also high.

Notch formation is not good because it affects uniform placement density. So we try to maximize the core width and height at the centre of the core area. So we should try to macro placement in such a way that the core area width/height should be maximum in the centre.

A notch formation is shown in the figure below by the red circled area. This can be avoided in the macro placement style used in first figure.

Notch formation in macro placement

Macro channel spacing 

The area between two close macros is termed macro channel spacing. In the macro channel, there will be standard cell placement and need a power connection. But if the macro spacing is too less, there is a chance that the power rails in not connected to power straps which is problematic.

Macro channel spacing

If there is area crunch we can abut two macros as shown on the right side of the image. But if we are not abutting the macro than between two macros the spacing should be minimum in which at least one VDD and VSS stripe should cross. If the channel width is too low so that no power strip crosses in this area then the rails of this region will not get power. The channel on the left side of the above figure is problematic as the standard cells seating in this region may lose PG connection.

Macro abutment

If required we can abut two macros as shown on the right side of the above figure. Only thing two remember while abutment is this pins should not be on the abutment edge. Pins should be on non-abbutment edge.

IO pins to macro spacing 

If there are no pins on the core boundary we can place the macro close to the boundary but on the boundary, there are io pins, we should place macro a with some spacing to avoid congestion near the pins. 

Halo over the macro

Halo is nothing but a placement blockage which are associated with macro, so if we move macro, the halo will move accordingly. To avoid the congestion on the edge of macro and also base DRC we avoid placing standard cells on the edge of the macro. A halo is put on the macro to block around the macro. 

Routing blockage over the macro

Macro designing needs some more metal layers as compared to standard cells. So the metal layers already used inside the macro can not be used for routing over macro and need to block over the macro. So we need routing blockage over the macro.

Partial placement blockage in macro channel and macro to io pins area

To avoid congestion in the macro channels, We apply partial placement blockage in the macro channel so that we can control the placement density. We can also apply the partial placement blockage in the region between io pins and macro as shown in the figure below. All yellow region is showing the partial placement blockage region, we can set the placement density in these regions.

Partial placement blockage

Macro placement is the most important part of PnR as the QoR strongly depends on the macro placement. The above-mentioned rules are standard rules which generally followed in macro dominating blocks. 

Thank You.

Pre-placement Activities in Physical Design

 In a broader sense, PnR (Place and Route) stage in physical design is basically Placement and Routing of all the instances present in the netlist in a defined core area in such a way that it should meet design rules and timing requirements. But before starting the actual automatic placement of instances by the PnR tool, there are certain activities which must be done prior to placement and those are called pre-placement activities. In this article, we will discuss some important pre-placement activities. 

Pre-placement activities in PnR

Major pre-placement activities:

• Pin placement
• Macro placement 
• Halo and routing blockage 
• Power plan
• Boundary cell/End cap cell placement
• Well tap cell placement
• Partial placement blockage /Density screen creation

Here we will discuss these activities in details in order as they needed to be performed. 

Pin placement:

In block-level PnR, input-output pins location are generally decided by the full-chip owner and the pin def is given to block owners. But some times pin location are not fixed at the top level and meanwhile block owner need to place them as per their convenience.

PnR tools provide a pin editing utility in their tools through which large numbers of pins can be placed easily. For innovus we can open the pin editor as Edit --> Pin Editor

Basically, we need to provide the following inputs to pin editor and corresponding image is shown a  typical pin placement.

 

 Pin list 

Metal layer 

Pin width

Pin depth

Side/edge

Spread / Distance between two pins 

 

Pin placement in PnR

Pins location could be either on edge of core or inside the core also. In case of pin def is available, we just need to defIn the pin.def file. In Innovus we can defIn the pin def file as bellow.

defIn <pin.def> 

Once all pins are placed, we can check that. In innovus we have a command. 

checkPinAssignment

The above command will give the total number of pins, the number of legal/illegal pins, the number of placed/unplaced pins.

Sometimes some i/o pins might have short with the PG structure, We can verify those shorts using following innovus command.

verify_PG_short -no_routing_blkg -no_cell_blkg

In case there are some shorts, we can fix those using following innovus command.

editPin -pin <pin name> -fixOverlap

Once all the pins are placed, we can defOut pins in a file for future use.

selectPin *    ;  Or   selectPin [dbGet top.terms]

defOut -selected <file_name>

Macro Placement:

Macro placement is a major step of the floorplan and the QoR (quality of result) of PnR is strongly dependent on the macro placement. A good macro placement requires thorough analysis of data flow in the block.
A bad floorplan could result in congestion and bad internal timings. There are some steps which must be followed especially in a macro dominating block. A detail discussion on macro placement strategy is explained in this article (will be linked soon).

Halo and Routing blockage:

Macros having high pins count near the edges generally and if the standard cell placement is high there, it could lead congestion. To avaoid this congestion we neet to put halo around the macro. (Halo is explained here - will be linked soon). The macro design needs more metal layers than normal standard cell and its pins are available in higher metal layers than the standard cells. So we need to put routing blockage for the layers which are used inside the macro. The power rails are blocked over the macros and power is delivered to the macros directly from power stripes.

Power Plan:

A power plan is a very robust power grid structure to deliver power to all macros and standard cells available in the design without much IR drop in the power grid. power grid takes power from bumps on the top metal layer and it delivers power to the lowest maetal layer in which standard cells follow pin available. 

From bumps, power goes to power stripe and power stripe delivers power to the VDD and VSS rails. Macros get power directly from power stripe as in place of macro there are no power rails drawn. 

Boundary cell placement:

Each placement row must be terminated with a boundary cell at both ends. Why we need boundary cells and what are the function of boundary cells, has been discussed in this article.

Well tap cell placement:

To get tap the psub to VSS and the nwell to VDD in order to avoid the latch-up issue in the design we need to place well tap cells at regular intervals in the core area. A detail discussion on well tap cells and its placement has been discussed in this article.

Partial placement blockage:

To avoid the congestion, we need to place partial placement blockage especially in the region where the pin density is more. We generally place partial placement blockage in the channel regions and the regions where io pins are placed. If the cell placement density will become high in this region, it may cause congestion as these areas already has lots of pin connections. 

Apart from these major activities, there are many other things which we need to on block specific like antenna cell placement, TCD Cells, PCLAMP cell placement. In the lower node, we need to check base DRC also after the macro placement steps. 

Thanks! 

Follow the blog for more updates.

Written Test Question for Physical Design Engineer: Question Set - 6

 

 Code: ALTRN0Y112020PD

Some companies take a written test sometimes to shortlist the candidates before the interview process. This is a common process if the applicants are large in numbers. In such written test, the format is MCQ and some short questions. 

We are very thankful to one of our follower who has appeared in this test and shared these questions based on memory. The purpose of sharing this question is only to provide the right guidance to the candidate who is going to appear in such a written test. I would encourage all the freshers to practice these question for their future test/Interview. I would also encourage to find the answer to these question either by own. There is no sense of proving the answer to these questions here. But if someone finds any question really difficult to solve and open discussion in the comment section. 

1. Hold slack equation 

2. Setup slack equation

 

3. When did hold analysis depends on the frequency of the clock 

a) half cycle path

b) single cycle path 

C) multicycle path 

d) it never depends 

4. While doing OCV which things are considered for setup analysis 

a) max launch path delay and min capture path delay

b) min launch path delay and max capture path delay 

c) max launch and capture path delay

d) min launch and capture path delay 

5. How to fix EM effect 

a) decreasing the space between metal layers 

b) decreasing straps 

c) increasing drive strength of the driver 

d) increasing space between metal layers 

6. Why do we add tap cells 

a) to maintain well continuity 

b) to prevent latch up  

c) to prevent DRC's 

d) all of the above 

7. Why do we add metal fillers 

a) to ensure etching properly 

b) to ensure density issues 

c) to increase the area of the chip 

d)to ensure well continuity 

8. If the schematic has 11 and layout is 10 nets then, what might be reason 

a) opens 

b) shorts

c) ERC

d) all of the above 

9. Numerical problem related to finding clock frequency 

10. Numerical problem related to finding slack 

11. High positive skew leads to

a) setup violation 

b) hold violation 

c) DRcs

d) all of the above 

12. In VLSI Design, CMP stands for? 

13. Numerical problem to find setup slack 

14. Nand and Nor gate logic diagram SOP forms

15. Setup uncertainty increases from placement to CTs

a) true 

b) false

c) based on SDC 

d) based on clock frequency 

16. Only clearing LVS leads to the proper functioning of the chip 

a) true 

b) false 

17. Numerical problem related to reg to reg data path delay calculation 

18. A CMOS circuit consumes only a significant amount of power during 

a) static state 

b) when cooling 

c) when warming

d) all of the above 

19. Routing congestion depends on which factors

a) ratio of required layers and available layers 

b) ratio of available and required 

c) depending on availability of metalayers 

d) none of the above 

20. Question related to ground bounce, power bounce and glitch 

21. Value of threshold voltage depends on

a) doping concentration 

b)distance between source and drain 

c) temperature 

d) all of the above 

22. Why we reorder scan chains during placement stage?

23. For multi-voltage blocks which power cells are used 

a) isolation cells

b) retention cells 

c) level shifters 

d) all

24. Which configuration is more preferable for floorplan 

a) double BACK  + channel width spacing 

b) without double back + channel width spacing 

c) double back + row alignment

d) none of the above 

25. Concept of fixing time violations by adjusting clock arrival times at the registers in the preCTS stage is called 

a) time borrowing 

b) managing skew 

c) maintaining timing 

d) none of the above 

26. While calculating standard cell utilization what are all will be considered 

a) macro + blockage + standard cell (area)

b) macro + blockage (area)

c) macro + physical cells + standard cells (area)

d) all of the above 

27. RV checks Are needed for 

28. Inputs for LVS

a) spice + netlist + rule deck

b) spice + rule deck + lib files 

c) OASIS + netlist + lib 

d) none of the above 

29. Via3 will connect which of the following metal layers 

a) 1 and 3

b) 2 and 3

c) 3 and 4

d) none 

 

30.  A 4-bit modulo 16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50 ns. The max. clock frequency that can be used is equal to

31. A pulse has a period of 15 ms. Its frequency is

32. A 8-bit successive approximation ADC has a full-scale reading of 2.55 volts and its conversion time for an analog input of 1 volt is 20 µs. The conversion time for a 2 volts input will be?

33 . How many binary numbers are required to represent a decimal number 748?

 34. DRC is used to 

a)to ensure chip fabrication

b)to ensure chip doesn't get heated 

c)to verify parasitics on chip

d) all of these 

35.  Antenna diodes are used for 

a) to protect the gate 

b) protect VDD and VSS

c) to protect the substrate 

d) all of the above

36.  Buffers are added to 

a) to fix timing violations 

b) to fix DRC

c) to fix parasitic values 

d) all 

37. Metal pitch and metal spacing are the same 

True

False

38. What is the effect of high drive strength buffer when added in the long net 

a) delay of net decreases

b) delay of net increases 

c) delay doesn't effect 

d) none of the above 

39. Cross talk glitch leads to 

a)timing failure 

b) functional failure 

c) substrate failure 

d)all of these 

40. Programmable special cells used during ECO

a) gate array filler cells

b) filler cells

c) metal fills 

d)decap cells 

41. What is a physical cell?

a) cell which doesn't have any functionality 

b)  cell is not synthesized 

c) cell which is inserted only in layout 

d) all of the above 

42. Power gating technique in low power is used to reduce 

a)static power 

b)leakage power 

c)internal power 

d) all of the above 

43. Which of the following is not present in SDC 

a) max cap

b) max trans 

c) max current density 

d) max fanout 

44. The phenomenon associated with transistor switching when the gate voltage may appear less than the local ground potential 

a) ground bounce 

b) supply bounce

c) glitch 

D) none 

45. Leakage recovery can be achieved through 

a)Hvt to Svt

b) Lvt to Hvt

C)Rvt to Lvt.

d) svt to lvt

46. Which of the following must be fixed during physical design 

a) floating inputs 

b) floating outputs 

C) floating metals 

d) both b and c 

47. Which slew value will be propagated to slew _out of slew _A is 100 ps and slew_B is 80ps for hold analysis 

a) 80 ps

b) 100 ps

c) 20 pls

d) 180 ps

48. A 16-bit modulo 16 ripple counter uses JK flops if propagation delay is 25 ns, the max frequency of the clock is 

a) 25

b) 10

c) 2

d) 16

49. Digital signals transmitted on a single conductor must be transmitted in 

a) serial 

b) digital 

C) slow speed 

d) none 

50. In a certain digital waveform, the period is four times the pulse width, the duty cycle of the waveform will be? 

51. Follow pin connections to the standard s are done in encounter through

a)z- route 

b)s-route 

c)trail route 

d) nano- route 

52.set Y[ ]; 

set Z[a,b,c]; 

lappend $Y,$Z;

What is the output 

a) empty list 

b) [a b]

c) [a b c]

d) none

[ Note: If you find any question has typo error or wrong, comment for the correction.]

 Thank you.

Synthesis and Physical Design Interview Questions: Question Set -5

Code: CYPR2Y102020PD

Introduction and Experiences

1. Self Introduction
2. Explain about the projects that you have worked on. (Type of work and tools used)

Synthesis

1. Explain about Synthesis flow and what happens at each stage. (Inputs required, elaboration, generic stage, mapping and optimization stages)
2. Explain about Synthesis Inputs. 
3. Differentiate between Logical and Physical Synthesis. (QoR impact between them)
4. Wire load model(WLM), Mode, Types of trees
5. Delay Calculation in WLM method. (Fanout based delay calculation)

 

Place and Route

1. What are Inputs for PnR and Initial Checks need to be done?
2. How to check for uniqueness of Netlist?
3. Explain stages in PnR.
4. Explain about useful skew and how it impacts the design.
5. How do we achieve a better insertion delay?
6. Explain about the CTS issues that you solved.
7. Explain Physical Cells at the transistor level.
8. Explain UPF, power domains, supply sets, isolation cells, retention registers.
9. Feedthru insertion procedure and minimizing them. How you did Partitioning and improved partition related size, ports creation, Congestion.

RTL

1. RTL Code for synchronous rst and asynchronous rst. (How do we write always block for this?)
2. How do you write RTL code for FSM? (Explain about the number of always blocks required and significance of each one)
3. Write RTL code for the traffic light system.

SignOff

1. Explain about the LEC procedure and issues faced and solved with respect to non-equivalent points.
2. How do we fix Setup and Hold time violations?
3. Explain about Dynamic and Leakage Power Consumption and methods to reduce them.
4. If the chip is fabricated and hold violation exists. So what will you do? (other than saying that chip won't work)
5. Scripting related to finding empty modules, Unix commands.

Post Credit: 

These questions are shared by one of our active group members. Thanks a lot for your contribution!!!